Annual report 2000 - Europractice

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Low cost IC prototyping The cost of producing a new ASIC for a dedicated application within a small market can be high, if directly produced by a commercial foundry. This is largely due to the 4 NRE (Non-Recurring Engineering) overheads associated with design, manufacturing and test. EUROPRACTICE has reduced the NRE, especially for ASIC prototyping, by two techniques: (i) Multi Project Wafer Runs or (ii) Multi Level Masks. Multi Project Wafer Runs By combining several designs from different customers onto one mask set and prototype run, known as Multi Project Wafer (MPW) runs, the high NRE costs of a mask set is shared among the participating customers. Fabrication of prototypes can thus be as low as 5% to 10% of the cost of a full prototyping wafer run. A limited number of tested or untested ASIC prototypes, typically 10-20, are delivered to the customer for evaluation, either as naked dies or as encapsulated devices. Only prototypes from fully qualified wafers are taken to ensure that the chips delivered will function “right first time”. In order to achieve this, extensive Design Rule and Electrical Rule Checkings are performed on all designs submitted to the Service. EUROPRACTICE is organising about 130 MPW runs per year in various technologies. Multi Level Mask Single User Runs Another technique to reduce the high mask costs is called Multi Level Mask (MLM). With this technique the available mask area (20 mm x 20 mm field) is typically divided in four quadrants (4L/R : four layer per reticle) whereby each quadrant is filled with one design layer. As an example : one mask can contain four layers such as nwell, poly, ndiff and active. The total number of masks is thus reduced by a factor of four. By adapting the lithographical procedure it is possible to use one mask four times for the different layers by using the appropriate quadrants. Using this technique the mask costs can be reduced by about 60%. The advantages of using MLM single user runs are : (i) lower mask costs, (ii) can be started any date and not restricted to scheduled MPW runs, (iii) single user and (iv) customer receives minimal a few wafers, so a few hundreds of prototypes. This technique is preferred over MPW runs when the chip area becomes large and when the customer wants to get a higher number of prototypes or preserie. When the prototypes are successful, this mask set can be used
Design kits Designers need the necessary information (design rules, electrical parameters, cell library, etc.) of the chosen technology before they can start the design phase. All this information is put together by the foundry in the so-called ‘design kit’. EUROPRACTICE distributes more than 55 different design kits and cell libraries of the supported technologies for most popular CAD tools (Cadence, Mentor Graphics, Synopsys, Tanner, etc.) on CD-ROM. Customers can have a copy of the CD-ROM with the cell libraries & design kits by signing a non-disclosure agreement with EUROPRACTICE. under certain conditions for low volume production. This technique is only available for technologies from Alcatal Microelectronics. Prototype testing and encapsulation In most of the cases our customers test their ASIC samples themselves. But for those who do not have this possibility we offer prototype testing. In order to set up a test solution, we need the test vectors. In order to make any electrical tests a test solution has to be established and information such as test vector set for functionality, foundry information for parametric test, pin out information, critical timing parameters and application specific test set-ups has to be provided. With this information the electrical test solution can be implemented. EUROPRACTICE ASIC service offers encapsulated prototypes. The packaging is done by industrial assembly houses and the range of prototype packages includes DIL, SOIC, CLCC, JLCC, PGA, BGA, CQFP, etc. For specific requirements, a solution will be found. Failure analysis In case the prototype does not meet the electrical specification or is not functionally correct, the failure has to be determined. The use of ATE, change in test vectors, E- beam test and Focused Ion Beam are examples of techniques to detect failures. Debug and repair It is important that some small design errors can be corrected in order to get working prototypes for demonstration in time or to avoid 5
Page 2 and 3: EUROPRACTICE IC service The right c
Page 4 and 5: 2 Table of contents Foreword 1 ASIC
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Page 10 and 11: EUROPRACTICE : Your One-Stop partne
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Page 22 and 23: ASIC for the intelligent house Appl
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Page 26 and 27: CUSTOMER TOWN Number of ASICs Unive
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Annual report 2000 - Europractice

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