Annual report 2000 - Europractice

EUROPRACTICE
offers deep submicron layout service
Deep submicron layout generation
is a difficult task. Lots of effects are
to be considered and can cause serious
problems for your circuits:
clock-skew, latency of interacting
clocks, IR-drop on power-distribution,
electro-migration problems,
delays caused by the interconnect,
handling 5 or more layers of metal
in the back-end.
EUROPRACTICE IC Service is
providing a deep submicron layout
service, starting from gate-level
netlist. The service includes clocktree
synthesis, and provides information
allowing the circuit designers
to verify accurate post-layout
timing using timing simulation or
Layout of 29 Kgates circuit with
11 RAM blocks in Alcatel Microelectronics
0.35µ CMOS (5-metallayers)
- 20 mm 2 (By courtesy of IMEC).
static-timing analysis. All information
is provided to automatically
update the circuit in an incremental
way, using in-place optimisation
in the synthesis tool. This can involve
buffer insertion, cell replacement,
and local re-synthesis. Placement-iterations
typically are done
within 24 hours, providing complete
feedback to redo all verifications.
With the Avant! tools, Europractice
addresses all of the above
mentioned problems.
Many circuits have been taped out
successfully, up to 6 metal-layer
processes, both for in-house developed
Systems-On-a-Chip, as for
ASICs developed by third party design
houses, research institutes and
universities. Several of the circuits
have been systems with analog full
custom blocks, combined with
other macro’s and memories. Procedures
are in place to offer standard
I/O configurations, staggered
I/O configurations, and configurations
with the bonding-pads equal-
Layout of a 130 Kgates circuit in UMC
0.18µ CMOS (6 layers of metal) - 4.5 mm 2
(By courtesy of IMEC).
ly spread over the standard-cell
core, for flip-chip application.
Circuit complexities handled were
up to several hundred thousands
of equivalent gates, system clockrates
up to 200 MHz. Typically,
layout and full verification is done
in 10-15 working days.
Layout of a mixed analog-digital circuit
with 130 Kgates in Alcatel Microelectronics
0.35µ CMOS (5-metallayers)
- 29 mm 2
(By courtesy of IMEC).
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