VHDL Made Easy! - Xilinx

38
Structured
Floorplanning
Continued from the previous page
Figure 5
Multiplexer
Floorplan
Layout 1, 2
bus bits
Figure 6
Multiplexer
Floorplan
Layout 2, 2
bus bits
knowledge of the design’s structure, a
truly optimized design can be achieved.
Figures 5 and 6 show two possible
floorplans for the multiplexer logic; where
bb_0 refers to the DATA bus bit 0 building
block, bb_1 refers to the DATA bus
bit 1 building block, and sop_0, sop_1
and or_0 refer to the combinatorial logic
shown in Figure 2. Both of these layouts
work reasonably well; they are small and
fit evenly into the allotted 2x24 CLC area.
The second layout has a slight advantage
in that the nets from the sop_0 and sop_1
instances to the or_0 instance will be of
equal length; thus, this floorplan will be
adopted.
Figure 7 Register Array Floorplan Layout (bottom half)
Next, the register arrays can be placed
in an manner that aligns them with the
multiplexers. In the XC8100 architecture, a
single D-type flip-flop (FD) requires two
adjacent CLCs in the same row, since it
uses the cascade connection between the
CLCs. There are four registers, requiring
eight CLCs, associated with each 4-to-1
multiplexer. Thus, a total of eight registers
(16 CLCs) are associated with the pair of
multiplexers located in the 2x3 cell area
shown in Figure 6.
Considering just the bottom-half of the
array, the multiplexer logic occupies the
bottom two rows, leaving six rows for
implementing their associated register
arrays. Since the multiplexers are arranged
in a configuration spanning three columns
(2x3 CLCs), and each register must be
constructed in a manner spanning two
columns (1x2 CLCs), it is convenient to
floorplan the register array in partitions
of six columns, encompassing two of the
2x3 multiplexer structures (four bit-slices).
Using this approach, the four building
block register arrays associated with the
four multiplexers will require 32 CLCs,
and need to be placed within a 6x6 CLC
area. A typically layout for this is implementation
is shown in Figure 7. This
layout keeps the registers that share a
common clock in the same set of rows,
with the exception of the registers that
share clk3, which are split between two
sets of rows.
Since the symbolic names for the
signals and instances are in a predetermined
numeric order, and the development
tools preserve these names, the
constraint file needed to implement this
basic floorplan for the whole design can
be generated by a short C program (see
page 39); this program could just as easily
have been written in awk, Perl, BASIC or
the constraints could be directly written
using a text editor.
The final step in the process is the
assignment of the clock signals to high
drive resources. This design uses four