FEBRUARY 2006 £3.80 - Index of
FEBRUARY 2006 £3.80 - Index of
FEBRUARY 2006 £3.80 - Index of
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INFO & MARKET NEWS & NEW PRODUCTS<br />
14<br />
New 16-bit XAP4 processor core<br />
Cambridge Consultants has<br />
released a new 16-bit RISC<br />
microprocessor IP core, which it<br />
will feature at the Design &<br />
Reuse IP-SoC conference in<br />
Grenoble, France on December<br />
7th and 8th 2005.<br />
The all-new 16-bit XAP4 features<br />
a modern, high-performance<br />
RISC architecture with low gate<br />
count, low power consumption<br />
and high code density. It is optimized<br />
for use in cost and performance<br />
sensitive ASIC designs<br />
and is available for evaluation<br />
now. On a 0.18 micron CMOS<br />
fabrication process, XAP4 can<br />
deliver up to 63 Dhrystone MIPS<br />
at a clock frequency <strong>of</strong> 117<br />
MHz. This benchmark performance<br />
<strong>of</strong> 0.54 MIPS/MHz is a<br />
50% improvement over Cambridge<br />
Consultants’ previous 16bit<br />
processor, XAP2, which has<br />
been manufactured in hundreds<br />
<strong>of</strong> millions by licensees such as<br />
CSR, and in ZigBee radios, automotive<br />
devices and low-power<br />
industrial and medical sensors.<br />
The XAP4 has both 16-bit data<br />
and address buses and is capable<br />
<strong>of</strong> running programs up to<br />
64 kBytes. The first implementation<br />
<strong>of</strong> the processor has a two-stage<br />
pipelined Von Neumann architecture.<br />
It is delivered to licensees as a<br />
s<strong>of</strong>t IP core in Verilog RTL that can<br />
be synthesized in as few as 12k<br />
gates for ASICs where die size<br />
and power consumption must be<br />
as small as possible. Cambridge<br />
Consultants has already delivered<br />
XAP4 to one licensee and is in discussion<br />
with other prospective cus-<br />
Advertisement<br />
tomers at present.<br />
The 16-bit XAP4 is the latest<br />
addition to Cambridge Consultants’<br />
microprocessor core lineup.<br />
There is also the 32-bit XAP3<br />
for more demanding applications,<br />
and in development is the<br />
XAP5 that also uses 16-bit data<br />
but extends the address bus to<br />
24-bits, providing support for<br />
larger program sizes up to 16<br />
Mbytes. All these processor cores<br />
include Cambridge Consultants’<br />
SIF debug logic, which provides<br />
full control over the processor<br />
and access to its debug registers,<br />
together with non-invasive access<br />
to any part <strong>of</strong> the processor’s<br />
memory map for data acquisition<br />
while a system is running.<br />
The architecture and design <strong>of</strong><br />
the XAP3, XAP4 and XAP5<br />
processors was conceived at<br />
Cambridge Consultants to fulfil<br />
the requirements <strong>of</strong> modern<br />
ASIC-based systems running<br />
code written by different programmers<br />
including real-time<br />
operating systems. All the<br />
processors include hardware<br />
support for privileged operating<br />
system modes where code running<br />
in user mode cannot corrupt<br />
supervisor or interrupt code.<br />
Code is position independent<br />
and there is also support for<br />
unaligned data access, making<br />
programs easy to port and quick<br />
to run. Most programs will be<br />
written in C and the processors<br />
feature direct support for many<br />
<strong>of</strong> the language constructs,<br />
which results in higher code density.<br />
There is hardware support<br />
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for rapid context switching, for<br />
example, when interrupts occur,<br />
and there are multi-cycle instructions<br />
to speed up multiply, divide<br />
and block copy operations.<br />
All <strong>of</strong> Cambridge Consultants’<br />
XAP microprocessors are supported<br />
by its xIDE integrated s<strong>of</strong>tware<br />
development and debug<br />
environment, which includes a<br />
programmer’s editor, assembler,<br />
debug interface, instruction set<br />
simulator, project build manager<br />
and GCC compiler, which provides<br />
the path for programming<br />
in C++. xIDE is quick and easy<br />
to install and use on Windows<br />
PCs, with Linux/Unix and Mac<br />
OS versions also available.<br />
xIDE can be customized to add<br />
features specific to a licensee’s<br />
ASIC or ASSP, and licensees can<br />
brand and deliver xIDE to their<br />
developers.<br />
Other advanced technical fea-<br />
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tures <strong>of</strong> the XAP3, XAP4 and<br />
XAP5 include: hardware support<br />
for operation as a slave processor<br />
when a master processor<br />
downloads a code image and<br />
bootstraps the XAP, support for<br />
multi-processor debug over SIF<br />
and architectures for combining<br />
XAP with Cambridge Consultants’<br />
APE signal processing engine,<br />
which <strong>of</strong>fers a dynamic data path<br />
routing capability. Details <strong>of</strong> the<br />
cores can be found at<br />
www.CambridgeConsultants.com<br />
/ ASIC,<br />
including trial downloads <strong>of</strong> the<br />
xIDE s<strong>of</strong>tware tools.<br />
Cambridge Consultants Ltd,<br />
Science Park, Milton Road,<br />
Cambridge, CB4 0DW, UK.<br />
Tel: +44 (0)1223 420024;<br />
Fax: +44 (0)1223 423373;<br />
www.cambridgeconsultants.com<br />
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(067016-6)<br />
elektor electronics - 2/<strong>2006</strong>