Basic Micro Studio Syntax Manual

Speeds
Processor Mode 0-4 Mode 5-7
BA 50 Kbps 100 Kbps
BAN 20 Kbps 40 Kbps
BAP 100 Kbps 380 Kbps
BAP40 400 Kbps 400 Kbps
ARC32 400 Kbps 400 Kbps
Commands
All SPI devices fall into 4 main transmission modes. They are specifi c to the timings of the writing and
reading of data. The write and read of data at the fi rst edge of the clock pulse is PRE. The second
edge of the clock pulse is POST. The PRE and POST edge of the clock will change depending on
whether the clock starts high(1) or low(0).
Most SPI device data sheets will indicate if they are PRE, POST, MSB or LSB. However in some
cases the data sheet might not be clear. So fi rst, we must determine if the data is read PRE or POST
clock edge. In almost all cases data can be written and read on the rising and falling edge of the
clock signal. Looking at the timing diagrams below the clock can start from one of two states high(1)
or low(0). The diagrams below illustrate the PRE and POST edge based on a high(1) or low(0) clock
start.
High(1) Clock Start
CLOCK
Low(0) Clock Start
PRE Edge
POST Edge
1 2 3 4 5 6 7 8
DATA D7 D6 D5 D4 D3 D2 D1 D0
CLOCK
DATA
PRE Edge
POST Edge
1 2 3 4 5 6 7 8
D7 D6 D5 D4 D3 D2 D1 D0
The diagrams for clock start show the data in both cases being written on the POST edge of the
clock. The next thing to determine is the bit order. Which from the diagram, starts with bit 7 (D7) and
ends with bit 0 (D0), this is MSB (Most Signifi cant Bit First). If the byte order were reversed and bit 0
(D0) was fi rst with bit 7 (D7) last that would be LSB (Least Signifi cant Bit First)
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