BSV by Example - Computation Structures Group

2.1.3 (* synthesize *)
Items contained within (* and *) are BSV attributes, used to guide the compiler in its decisions.
The (*synthesize*) attribute specifies that the module that follows is synthesized separately into a
hardware (Verilog) module. The top-level module of a design must be a synthesis boundary. Interior
modules can also represent synthesis boundaries. The design in this example has only one module.
You can also use the -g command-line flag when compiling to specify modules that are synthesis
boundaries, but we recommend using the (* synthesize *) attribute in the source text instead.
2.1.4 Module definition
The statement:
module mkTb (Empty);
defines a module named mkTb providing an Empty interface. By convention, we call our modules
“mkFoo”, for “make Foo”, to suggest that the module can be instantiated multiple times, possibly
with different parameters. Empty is a pre-defined interface with no methods. The keyword Empty is
not required, the statement could also be written as:
module mkTb();
BSV does not have input, output, and inout pins like Verilog and VHDL. Signals and buses are
driven in and out of modules with methods; these methods are grouped together into interfaces. An
Empty interface has no inputs or outputs.
Modules and interfaces form the heart of BSV. Modules and interfaces turn into actual hardware.
A module consists of three things: state, rules that operate on that state, and an interface to
the outside world (surrounding hierarchy). A module definition specifies a scheme that can be
instantiated multiple times.
2.1.5 Rule
The statement:
rule greet;
$display ("Hello World!");
$finish (0);
endrule
defines a rule named greet with no explicit rule condition. (An explicit rule condition is a boolean
expression in parentheses after the rule name; when omitted, it defaults to True.)
Rules are used to describe how data is moved from one state to another, instead of the Verilog
method of using always blocks. Rules have two components:
• Rule conditions: Boolean expressions which determine when the rule is enabled.
• Rule body: a set of actions which describe state transitions
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