BSV by Example - Computation Structures Group

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• Module m2 provides interface M2_ifc • Module m3 uses interface M2_ifc • Module m1b provides interface M1_ifc The top-level module mkTb, instantiates an instance m3 of the module mkM3: package Tb; (* synthesize *) module mkTb (Empty); Empty m3
Wherever mkM2 is instantiated, the actual parameter must be a static (compile-time) value. The statement: M1_ifc m1a
Page 1 and 2: BSV by Example The next-generation
Page 3 and 4: 3.6.3 UInt#(n) . . . . . . . . . .
Page 5 and 6: 10 Advanced types and pattern-match
Page 7 and 8: A.6.1 Scheduling error due to paral
Page 9 and 10: 1 Introduction BSV (Bluespec System
Page 11 and 12: • Haskell, for more advanced type
Page 13 and 14: would be unnecessary if sequential
Page 15 and 16: A few examples span multiple sectio
Page 17 and 18: In this simple example, the name of
Page 19 and 20: 2.2.4 Create a project file Figure
Page 21 and 22: This next example looks at a design
Page 23 and 24: • ActionValue Methods: These meth
Page 25 and 26: Another example: the Ord typeclass
Page 27 and 28: cannot automatically convert from a
Page 29 and 30: $display("maxInt16/4 = %x", maxInt1
Page 31 and 32: 3.9 Strings Source directory: data/
Page 33 and 34: 4.1.3 Value initialization from a V
Page 35 and 36: ActionValue #(Coord) g = s.response
Page 37 and 38: if (pack(cycle)[1:0] == 3) a = a +
Page 39 and 40: package Tb; (* synthesize *) module
Page 41 and 42: In BSV, the logical sequence of rul
Page 43 and 44: These are both legal final states o
Page 45 and 46: ule r1; x2
Page 47 and 48: Because of the rule condition if (v
Page 49: 6 Module hierarchy and interfaces 6
Page 53 and 54: Window Bluespec Development Worksta
Page 55 and 56: 6.3.1 The let statement This statem
Page 57 and 58: module mkTb (Empty); Dut_ifc dut 0
Page 59 and 60: interface Put_int; method Action pu
Page 61 and 62: module mkStimulusGen (Client_int);
Page 63 and 64: interface Server#(type req_type, ty
Page 65 and 66: Conflicts are discussed in more det
Page 67 and 68: (* descending_urgency = "r1, r2, r3
Page 69 and 70: Figure 6: Execution Order Graph As
Page 71 and 72: If you compile with the mutually_ex
Page 73 and 74: (* preempts = "(the_bar.r1, (r2, r3
Page 75 and 76: However, the rule calls dut.put() a
Page 77 and 78: After you compile and observe the r
Page 79 and 80: Sometimes, splitting a rule syntact
Page 81 and 82: Note that in each cycle, with respe
Page 83 and 84: interface Counter; method int read(
Page 85 and 86: noAction is a special null Action (
Page 87 and 88: In this example, the four lines enu
Page 89 and 90: Notice that the default value on bo
Page 91 and 92: ule doit; case (tuple2 (rw_incr.wge
Page 93 and 94: method Action enq(v) if (enq_ok); r
Page 95 and 96: In the next few examples we’ll cr
Page 97 and 98: Common Overloading Provisos Proviso
Page 99 and 100: module mkPlainReg2( Reg#(Bit#(n)) )
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Since type_b is a different type th
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• The optional deriving Eq clause
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color0 color1 color2 8 bits 8 bits
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A common example of a tagged union
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The simple processor module contain
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defines instruction addresses to be
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typedef struct { Reg#(int) ra; Reg#
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Functions like tuple2 are ordinary
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At every state, it tries to reduce
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Reg#(int) cycle
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• Z a wire that is not driven at
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These function expressions can be u
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Reg#(int) arr3[4]; for (Integer i=0
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to produce a vector of 4 elements (
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We can then use the genWith vector
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The output is: 13.4 Whole register
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Error: "Tb.bsv", line 20, column 35
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We’ll take a simple approach and
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arr[5]
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Reg#(int) counter
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ule stateIdle ( state[idle] == 1 );
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statement times (the number of cloc
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function Action functionOfAction( i
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action $display("Enq 10 at time ",
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Warning: "Tb.bsv", line 36, column
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module SizedFIFO(V_CLK, V_RST_N, V_
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• Every import "BVI" wrapper must
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The Verilog parameters, inputs, and
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A Source Files Complete, compilable
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package DeepThought; interface Ifc_
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rule step3 ( step == 3 ); $display(
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Reg#(int) step
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(* synthesize *) module mkTb (Empty
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method Action send (int a); f1.enq
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endmodule // ----------------------
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Copyright 2010 Bluespec, Inc. All r
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interface Put_int put_response; end
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f_out.enq (y); endrule interface re
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endrule rule enq2 (state > 4); f.en
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(* synthesize *) module mkGadget (S
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cycle
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(* descending_urgency = "r1, r2" *)
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$display ("%0d: Enqueuing %d into f
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A.7 RWires and Wire types Chapter e
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endrule method int read(); return v
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Version 2 of the counter (* synthes
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method Action decrement (int dd); v
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-----------------------------------
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-----------------------------------
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ule decr2 (state > 3); c2.decrement
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ule e; let x = state * 10; f.enq (x
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endfunction function Bool isBlock(
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method Action drive(tx ina, ty inb)
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package Tb; import SimpleProcessor:
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Reg#(InstructionAddress) pc
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$display("=== step 0 ==="); $displa
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endrule endmodule: mkTb endpackage:
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it o = 0; for (Bit#(2) i=0; i
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step
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endfunction Vector#(16,bit) bar2 =
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Reg#( Vector#(10,Status) ) regstatu
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endmodule: mkTb endpackage: Tb A.12
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A top-level module connecting the s
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functionOfAction( 30 ); // Create a
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endseq endpar $display("Par block d
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endmodule schedule first SB (clear,
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BSV by Example - Computation Structures Group

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