BSV by Example - Computation Structures Group

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A.12.4 Whole register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 A.12.5 Register containing a vector vs. vector of registers . . . . . . . . . . . . . . . 226 A.12.6 Vector of modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 A.12.7 Static elaboration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 A.13 Finite State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 A.13.1 Building a FSM explicitly using rules . . . . . . . . . . . . . . . . . . . . . . 230 A.13.2 One-hot FSM explicitly using rules . . . . . . . . . . . . . . . . . . . . . . . . 231 A.13.3 StmtFSM - Basic template . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 A.13.4 AutoFSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 A.13.5 StmtFSM example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 A.14 Importing existing RTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 A.14.1 Verilog File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 A.14.2 Using an existing interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 A.14.3 Defining a new interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 8
1 Introduction BSV (Bluespec SystemVerilog) is a language used in the design of electronic systems (ASICs, FPGAs and systems). BSV is used across the spectrum of applications—processors, memory subsystems, interconnects, DMAs and data movers, multimedia and communication I/O devices, multimedia and communication codecs and processors, signal processing accelerators, high-performance computing accelerators, etc. BSV is also used across markets—from low-power, portable consumer items to enterprise-class server-room systems. Being both a very high-level language as well as fully synthesizable to hardware, it is used in many design activities, as described below. This combination of high level and full synthesizability enables many of these activities that were previously only done in software simulation now to be moved easily to FPGA-based execution (whether the design is eventually bound for ASICs or FPGAs). This can speed up execution by three to six orders of magnitude (1000x to 1,000,000x). Such a dramatic speedup not only accelerates existing activities, but enables new activities that were simply not feasible before (such as cycle-accurate multi-core processor architecture models running real operating systems and real applications). 1.1 Design activities where BSV is used Executable Specifications (synthesizable). For today’s complex systems, a specification written in a human language (like English) is likely to be imprecise, incomplete or even infeasible and selfcontradictory in its requirements. A specification in BSV addresses these concerns, because of its precise semantics and executability on real data. Fleshing out a spec in this way is also called spec validation. Virtual Platforms (synthesizable). Today’s chips are dominated by the volume and complexity of the software that runs on them. It is no longer acceptable to have to wait for chips to be available before developing software. Virtual Platforms enable software development and testing to begin as early as day one. Virtual platforms written in BSV, being synthesizable, run on FPGAs at much higher speeds and greater accuracies than traditional software virtual platforms, greatly increasing software development productivity. Architectural Modeling (synthesizable). Complex SoCs (Systems on a Chip) involve complex tradeoffs. What should be done in SW vs. in HW accelerators? How many processors vs. HW accelerators? What micro-architecture for processors, interconnect, memory systems? These decisions will affect chip area, speed, power consumption, cost, and time-to-market. Many of these decisions are too complex to be taken analytically—they require actual execution on actual data. BSV is used for synthesizable architecture models, exploration and validation at the system, subsystem, and the IP block levels. Design and Implementation. This is the classic design activity of IP blocks (Intellectual Property), except that today these can be complex subsystems. BSV enables designing such components at a much higher level of abstraction and with better maintainability. Verification Environments (synthesizable). Every verification environment is a model of “the rest of the system.” As such, they can be as complex as designs themselves, face similar speed-of-execution issues, and face similar issues of reusability, maintainability and evolvability. BSV is used for writing synthesizable transactors, testbenches and both system and reference models. 1.2 Key ideas in BSV BSV borrows powerful ideas that have been developed over several decades in advanced formal specification and programming languages. These can be classified into two groups—behavior and structure. 9
Page 1 and 2: BSV by Example The next-generation
Page 3 and 4: 3.6.3 UInt#(n) . . . . . . . . . .
Page 5 and 6: 10 Advanced types and pattern-match
Page 7: A.6.1 Scheduling error due to paral
Page 11 and 12: • Haskell, for more advanced type
Page 13 and 14: would be unnecessary if sequential
Page 15 and 16: A few examples span multiple sectio
Page 17 and 18: In this simple example, the name of
Page 19 and 20: 2.2.4 Create a project file Figure
Page 21 and 22: This next example looks at a design
Page 23 and 24: • ActionValue Methods: These meth
Page 25 and 26: Another example: the Ord typeclass
Page 27 and 28: cannot automatically convert from a
Page 29 and 30: $display("maxInt16/4 = %x", maxInt1
Page 31 and 32: 3.9 Strings Source directory: data/
Page 33 and 34: 4.1.3 Value initialization from a V
Page 35 and 36: ActionValue #(Coord) g = s.response
Page 37 and 38: if (pack(cycle)[1:0] == 3) a = a +
Page 39 and 40: package Tb; (* synthesize *) module
Page 41 and 42: In BSV, the logical sequence of rul
Page 43 and 44: These are both legal final states o
Page 45 and 46: ule r1; x2
Page 47 and 48: Because of the rule condition if (v
Page 49 and 50: 6 Module hierarchy and interfaces 6
Page 51 and 52: Wherever mkM2 is instantiated, the
Page 53 and 54: Window Bluespec Development Worksta
Page 55 and 56: 6.3.1 The let statement This statem
Page 57 and 58: module mkTb (Empty); Dut_ifc dut 0
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interface Put_int; method Action pu
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module mkStimulusGen (Client_int);
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interface Server#(type req_type, ty
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Conflicts are discussed in more det
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(* descending_urgency = "r1, r2, r3
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Figure 6: Execution Order Graph As
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If you compile with the mutually_ex
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(* preempts = "(the_bar.r1, (r2, r3
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However, the rule calls dut.put() a
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After you compile and observe the r
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Sometimes, splitting a rule syntact
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Note that in each cycle, with respe
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interface Counter; method int read(
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noAction is a special null Action (
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In this example, the four lines enu
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Notice that the default value on bo
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ule doit; case (tuple2 (rw_incr.wge
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method Action enq(v) if (enq_ok); r
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In the next few examples we’ll cr
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Common Overloading Provisos Proviso
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module mkPlainReg2( Reg#(Bit#(n)) )
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Since type_b is a different type th
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• The optional deriving Eq clause
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color0 color1 color2 8 bits 8 bits
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A common example of a tagged union
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The simple processor module contain
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defines instruction addresses to be
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typedef struct { Reg#(int) ra; Reg#
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Functions like tuple2 are ordinary
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At every state, it tries to reduce
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Reg#(int) cycle
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• Z a wire that is not driven at
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These function expressions can be u
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Reg#(int) arr3[4]; for (Integer i=0
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to produce a vector of 4 elements (
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We can then use the genWith vector
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The output is: 13.4 Whole register
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Error: "Tb.bsv", line 20, column 35
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We’ll take a simple approach and
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arr[5]
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Reg#(int) counter
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ule stateIdle ( state[idle] == 1 );
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statement times (the number of cloc
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function Action functionOfAction( i
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action $display("Enq 10 at time ",
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Warning: "Tb.bsv", line 36, column
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module SizedFIFO(V_CLK, V_RST_N, V_
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• Every import "BVI" wrapper must
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The Verilog parameters, inputs, and
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A Source Files Complete, compilable
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package DeepThought; interface Ifc_
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rule step3 ( step == 3 ); $display(
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Reg#(int) step
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(* synthesize *) module mkTb (Empty
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method Action send (int a); f1.enq
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endmodule // ----------------------
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Copyright 2010 Bluespec, Inc. All r
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interface Put_int put_response; end
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f_out.enq (y); endrule interface re
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endrule rule enq2 (state > 4); f.en
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(* synthesize *) module mkGadget (S
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cycle
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(* descending_urgency = "r1, r2" *)
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$display ("%0d: Enqueuing %d into f
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A.7 RWires and Wire types Chapter e
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endrule method int read(); return v
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Version 2 of the counter (* synthes
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method Action decrement (int dd); v
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-----------------------------------
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-----------------------------------
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ule decr2 (state > 3); c2.decrement
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ule e; let x = state * 10; f.enq (x
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endfunction function Bool isBlock(
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method Action drive(tx ina, ty inb)
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package Tb; import SimpleProcessor:
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Reg#(InstructionAddress) pc
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$display("=== step 0 ==="); $displa
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endrule endmodule: mkTb endpackage:
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it o = 0; for (Bit#(2) i=0; i
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step
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endfunction Vector#(16,bit) bar2 =
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Reg#( Vector#(10,Status) ) regstatu
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endmodule: mkTb endpackage: Tb A.12
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A top-level module connecting the s
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functionOfAction( 30 ); // Create a
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endseq endpar $display("Par block d
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endmodule schedule first SB (clear,
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BSV by Example - Computation Structures Group

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