ug585-Zynq-7000-TRM

Table 10‐3: DDR I/O Signal Pin List
Device Pin Name I/O
DDR_VR{P,N} ~ X X X
10.2 AXI Memory Port Interface (DDRI)
10.2.1 Introduction
Chapter 10: DDR Memory Controller
Each AXI master port has an associated slave port in the arbiter. The command FIFO located inside
the port stores the address, length and ID contained in the command. The RAM in the write port
stores the write data and byte enable. The RAM in the read port stores the read data coming back
from the core.
Because the read data coming back from the core can come out of order, the RAM is used for data
re-ordering. Each AXI command can make a request (write or read) for up to 16 data transfers (up to
the AXI limit). A single command coming from the AXI can be split into multiple requests going to
the arbiter logic and the controller.
The incoming command is first stored in the command FIFO. After a valid command is detected in
the write or read port, the value of the length field is checked and the number of requests associated
with this command is calculated. The logic then sends arbiter requests to the arbitration logic. The
arbitration logic looks at the requests from all the ports and gives the grant to one port at a time.
When a write port receives the grant from the arbiter, it generates write address, and write data
pointer and asserts the command valid. A read port on receiving grant generates read address, read
command length and the read token and asserts the command valid. Requests from various ports are
multiplexed using the grant signal.
When a write command is accepted by the DDR controller, it sends the write data pointer back to the
arbiter. The write data from all ports is multiplexed using the port ID contained in the write data
pointer.
When the read data comes back from the core, an associated ID is used direct the data to the
appropriate read port. According to AXI specifications, the read data with the same ID is required to
be given back to the AXI read master in the same order in which read commands were received by
the port.
DDRI Features:
Connections
DDR2 LPDDR2 DDR3
DDR_VREF{0,1} ~ X X Voltage reference
DCI voltage reference. Used to calibrate input termination.
and DDR I/O drive strength. Connect DDR_VRP to a resistor
to GND. Connect DDR_VRN to a resister to VCC_DDR.
• Four identical 64-bit AXI ports support INCR and WRAP burst types
• Sophisticated arbitration schemes to prevent data starvation
• Low latency path using urgent bit to bypass arbitration logic
Description
Zynq‐7000 EPP Technical Reference Manual www.xilinx.com 214
UG585 (v1.2) August 8, 2012