ug585-Zynq-7000-TRM

Table 2‐9: PL Interrupt Signals
Type PL Signal Name I/O Destination
PL to PS
Interrupts
PS to PL
Interrupts
2.6.3 Event Signals
IRQF2P[7:0] I SPI: Numbers [68:61].
IRQF2P[15:8] I SPI: Numbers [91:84].
IRQF2P[19:16] I PPI: nFIQ, nIRQ (both CPUs).
IRQP2F[27:0] O
Chapter 2: Signals, Interfaces, and Pins
Pl Logic. These signals are received from the I/O peripherals and are
forwarded to the interrupt controller. These signals are also provided as
outputs to the PL.
The PS supports processor events to and from the PL (see Table 2-10). These signals are
asynchronous to the PS and FCLK clocks. For details on these signals, see Chapter 3, Application
Processing Unit.
Table 2‐10: PL Event Signals
Type PL Signal Name I/O Description
Events
Standby
EVENTEVENTI I Causes one or both CPUs to wakeup from a WFE state.
EVENTEVENTO O Asserted when one of the CPUs has executed the SEV instruction.
EVENTSTANDBYWFE[1:0] O CPU standby mode: asserted when a CPU is waiting for an event.
EVENTSTANDBYWFI[1:0] O
CPU standby mode: asserted when a CPU is waiting for an
interrupt.
2.6.4 Idle AXI, DDR Urgent/Arb, SRAM Interrupt Signals
The idle AXI signal to the PS is used to indicate that there are no outstanding AXI transactions in the
PL. Driven by the PL, this signal is one of the conditions used to initiate a PS bus clock shut-down by
ensuring that all PL bus devices are idle.
The DDR urgent/arb signal is used to signal a critical memory starvation situation to the DDR
arbitration for the four AXI ports of the PS DDR memory controller.
Table 2‐11: PL AXI Idle, DDR Urgent/Arb and SRAM Interrupt Signals
Type PL Signal Name I/O Destination Reference
Idle PL AXI interfaces FPGAIDLEN I
DDR Urgent Signal DDRARB[3:0] I
SRAM EMIOSRAMINTIN I
Central interconnect
clock disable logic
DDR memory
controller
Chapter 10, DDR Memory Controller
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UG585 (v1.2) August 8, 2012