ug585-Zynq-7000-TRM

14.2 Block Diagram
X-Ref Target - Figure 14-1
As shown in Figure 14-1, the GPIO module is divided into four banks:
• Bank0: 32-bit bank controlling MIO pins[31:0]
• Bank1: 22-bit bank controlling MIO pins[53:32]
Note: Bank1 is limited to 22 bits because the MIO has a total of 54 pins.
• Bank2: 32-bit bank controlling EMIO signals[31:0]
• Bank3: 32-bit bank controlling EMIO signals[63:32]
Chapter 14: General Purpose I/O (GPIO)
The GPIO is controlled by software through a series of memory-mapped registers. The control for
each bank is the same, although there are minor differences between the MIO and EMIO banks due
to their differing functionality.
Restrictions
GPIO
Bank
0
GPIO
Bank
1
GPIO
Bank
2
GPIO
Bank
3
32b
22b
32b
32b
Figure 14‐1: GPIO Block Diagram
UG585_c14_01_022212
The 7z010 CLG225 device supports 32 MIO pins as shown in the MIO table in section
2.4.4 MIO-at-a-Glance Table.
Zynq‐7000 EPP Technical Reference Manual www.xilinx.com 294
UG585 (v1.2) August 8, 2012
MIO
EMIOGPIOI[31:0],
EMIOGPIOO[31:0],
EMIOGPIOTN[31:0]
x 54
EMIO Interface to PL
EMIOGPIOI[63:32],
EMIOGPIOO[63:32],
EMIOGPIOTN[63:32]