ug585-Zynq-7000-TRM

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25.1.2 Clock Generation Chapter 25: Clocks During normal operation, the PLLs are enabled, driven by the PS_CLK clock pin. In bypass mode, the clock signal on the PS_CLK pin provides the source for the various clock generators instead of the PLLs. (Refer to the applicable Zynq-7000 EPP data sheet for PS_CLK characteristics.) When the PS_POR reset signal deasserts, the PLL bypass boot mode pin is sampled and selects between PLL bypass and PLL enabled for all three PLLs. The bypass mode runs the system significantly slower than normal mode, but is useful for low-power applications and debug. After the boot process and when the user code executes, the bypass mode and output frequency of each PLL can be individually controlled by software. The clock generation paths include glitch-free multiplexers and glitch-free clock gates to support dynamic clock control. Three Programmable PLLs • Single external reference clock input for all three PLLs ° ° ARM PLL: Usual clock source for the CPUs and the interconnect DDR PLL: Usual clock for the DDR DRAM controller and AXI_HP interfaces ° I/O PLL: Usual clock for I/O peripherals • Individual PLL bypass control and frequency programming • Shared bandgap reference voltage circuit for VCOs Clock Branches • Six-bit programmable frequency dividers • Dynamic switching on most clock circuits • Four clock generators for the PL 25.1.3 Reset The clock subsystem is an integral part of the PS and is reset when the system is reset. When this occurs, all of the registers that control the clocking module return to their reset values. Zynq‐7000 EPP Technical Reference Manual www.xilinx.com 514 UG585 (v1.2) August 8, 2012
25.1.4 System Viewpoint X-Ref Target - Figure 25-2 TAG DMAC Figure 25-1 shows the clock network and related domains from a system viewpoint. M0 IOP 32-Bit CPU_1x S0 A9 MP Core 32K I-Cache 32L D-Cache M0 S0 M1 I-AXI D-AXI Coherent TAG CTRL S1 GIC M1 S0 L-2 Cache Controller 512 KB Cache M0 AS M1 Async QoS S2 QoS S0 QoS US/UZ Top Bus Switch Snoop Control Unit (SCU) M0 S0 DS 256 KB OCM RAM A9 MP Core 32K I-Cache 32L D-Cache M0 M1 CORE (3x3) 64-Bit CPU_2x M2 AS Async Bridge I-AXI D-AXI Coherent M0 ACP AXI S1 UZ M1 DS/DZ Async Bridge M0 ACP EVT 2x1 OCM Switch 64-bit CPU_2x s1 Async Bridge S0 S1 S2 S3 Peripheral + PL Interrupts S0 AS FPGA_M 32-Bit CPU_2x Figure 25‐2: System Clock Domains Chapter 25: Clocks UG585_c25_02_041612 Zynq‐7000 EPP Technical Reference Manual www.xilinx.com 515 UG585 (v1.2) August 8, 2012 M0 S1 DS/DZ S0 FPGA_S 32-Bit CPU_2x DDR Controller M2 M1 US M0 US EVENT S0 US S1 AS S2 AS S3 US M0 AS M1 AS M2 DS M3 Peripheral APB S3 S2 S1 S0 CPU CLK (CPU_6x, CPU_2x, and CPU_1x) AS: Async Domain US: Up Sync DS: Down Sync UZ: Up Size DZ: Down Size DVC AFI AFI AFI AFI M0 M1 M2 M3 M0 M1 DAP AXI_HP 64/32 S1 S0 Peripheral Interrupts DDR 3X CLK DDR 2X CLK FPGA CLKs PL M0 Event
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Zynq-7000 EPP Technical Reference M
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Date Version Revision 06/25/12 1.1
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Chapter 3: Application Processing U
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6.2.4 Reset Requirements . . . . .
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10.2.2 Block Diagram . . . . . . .
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13.2.9 FIFO Overrun and Underrun Co
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16.1.2 Features . . . . . . . . . .
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Chapter 20: I2C Controller 20.1 Int
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25.8 GPIO and I2C Clocks . . . . .
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Chapter 31: PCI Express 31.1 Introd
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Introduction 1.1 Overview Chapter 1
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The Zynq-7000 system is composed of
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TrustZone Capabilities Chapter 1: I
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DDR Controller Core and Transaction
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• IEEE 802.3-2008 and IEEE 1588 r
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UART Controllers (Two) Chapter 1: I
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° ° Chapter 1: Introduction High-
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° ° Two, 32-bit slave interfaces
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XADC VCCADC, GNDADC N/A Analog powe
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X-Ref Target - Figure 2-2 AHB Maste
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X-Ref Target - Figure 2-3 PS Centra
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• Width of NAND Flash limited to
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Chapter 2: Signals, Interfaces, and
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Table 2‐7: PL‐PS Signal Groups
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2.6.5 DMA Req/Ack Signals Chapter 2
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Application Processing Unit 3.1 Int
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3.1.2 System‐level View Chapter 3
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3.2 Cortex A9 Processors 3.2.1 Summ
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Memory Access Sequence When the pro
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A TLB entry matches when these cond
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• Large, shared register file, ad
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Table 3‐1: Cache Controller Behav
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Full Line of Zero Write Chapter 3:
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Table 3‐3: ACP Read and Write Beh
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3.6 Support for TrustZone Within th
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These are a few notes about the Tru
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Notes: PL AXI Interface Note Chapte
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Table 4‐3: SLCR Register Map (Con
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4.7 Miscellaneous PS Registers The
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Interconnect Masters The interconne
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L2 Cache Controller Chapter 5: Inte
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X-Ref Target - Figure 5-2 Chapter 5
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Table 5‐3: Slave Visible AXI ID V
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Chapter 5: Interconnect (through L2
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5.3.3 Functional Description Chapte
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Table 5‐6: Additional per-port HP
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Chapter 5: Interconnect For the 32-
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5.3.9 Performance Optimization Summ
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5.5 AXI_GP Interfaces 5.5.1 Feature
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Table 5‐8: AXI Signals Summary (C
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Table 5‐8: AXI Signals Summary (C
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Chapter 6: Boot and Configuration
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Table 6‐2: Boot_Mode Strapping MI
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Chapter 6: Boot and Configuration J
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6.3.2 BootROM Header Chapter 6: Boo
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Start of Execution — Byte Offset
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Chapter 6: Boot and Configuration G
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Table 6‐6: NAND MIO Pins Signal N
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Chapter 6: Boot and Configuration 1
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Chapter 6: Boot and Configuration T
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6.3.6 Debug Status Chapter 6: Boot
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Table 6‐10: BootROM Modified Regi
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X-Ref Target - Figure 6-6 pcap_2xcl
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6.4.4 Device Configuration Flow PS
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Chapter 6: Boot and Configuration b
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The configuration flow is: 1. Devic
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7.1.1 Private, Shared and Software
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7.2 Functional Description 7.2.1 So
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Table 7‐3: PS and PL Shared Perip
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7.3.1 Write Protection Lock Down Ch
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Timers 8.1 Introduction Chapter 8 E
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Chapter 8: Timers Although peripher
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8.4.2 Block Diagram A block diagram
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8.5 Triple Timer Counters (TTC) Cha
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Chapter 8: Timers Overflow mode: Th
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Chapter 8: Timers 2. Set overflow h
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DMA Controller 9.1 Introduction Cha
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Chapter 9: DMA Controller ° Signal
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9.1.3 Block Diagram X-Ref Target -
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Reset Initialization Interface Chap
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X-Ref Target - Figure 9-4 CPU_3x2x
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9.2.3 Memory to/from PL Peripheral
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Chapter 9: DMA Controller specifies
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Chapter 9: DMA Controller The DMALD
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Table 9‐2: Event/Interrupt Resour
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Table 9‐4: Abort Handling Thread
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Table 9‐8: Security Usage Summary
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9.3.3 Reset Initialization Interfac
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Chapter 9: DMA Controller 9.5 Instr
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9.6.2 Memory to Memory Chapter 9: D
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Table 9‐15: Unaligned Transfers (
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# Only loopback if servicing a burs
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Chapter 9: DMA Controller For examp
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When a discontinuity in the source
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DDR Memory Controller 10.1 Introduc
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X-Ref Target - Figure 10-1 Chapter
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Table 10‐1: Connectivity Limitati
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• Deep read and write command acc
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X-Ref Target - Figure 10-4 DDR Inte
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X-Ref Target - Figure 10-5 10.4.1 P
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X-Ref Target - Figure 10-6 Aging Co
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X-Ref Target - Figure 10-8 DDR Inte
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Chapter 10: DDR Memory Controller I
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10.5.1 Loopback Chapter 10: DDR Mem
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Table 10‐7: Calibration Field Nam
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10.6.4 DDR Controller Register Prog
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Chapter 10: DDR Memory Controller a
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Automatic Training The standard tra
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10.7 Register Overviews Chapter 10:
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Table 10‐11: DDRI Registers Overv
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Operating Modes Chapter 10: DDR Mem
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10.9.4 Self Refresh Chapter 10: DDR
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11.1.1 Features Chapter 11: Static
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11.1.3 Notices 7z010 CLG225 Device
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11.3 I/O Signals Chapter 11: Static
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X-Ref Target - Figure 11-5 SMC Cont
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Quad‐SPI Flash Controller 12.1 In
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Chapter 12: Quad‐SPI Flash Contro
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Table 12‐2: Ignored AXI Read Addr
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12.3 Programming Guide Example: Sta
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Example: Read Data Sequence In this
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CPU_1x Clock Chapter 12: Quad‐SPI
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X-Ref Target - Figure 12-5 Dual SS,
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12.5.2 MIO Programming Chapter 12:
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a. Route Quad-SPI feedback clock ou
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X-Ref Target - Figure 13-1 AHB Inte
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• CRC generator and checker (CRC7
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Read Chapter 13: SD/SDIO Peripheral
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The sequence for data transfers wit
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Chapter 13: SD/SDIO Peripheral Cont
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13.3.4 Using ADMA X-Ref Target - Fi
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X-Ref Target - Figure 13-6 Synchron
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13.3.8 Bus Voltage Translation Chap
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Chapter 13: SD/SDIO Peripheral Cont
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14.2 Block Diagram X-Ref Target - F
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MIO bank control (for Bank0 and Ban
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Chapter 14: General Purpose I/O (GP
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Chapter 15: USB Host, Device, and O
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15.3.1 Block Diagram Chapter 15: US
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15.5 Host Data Structure X-Ref Targ
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15.6.2 DMA Engine X-Ref Target - Fi
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15.6.5 Port Controller X-Ref Target
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The change is a fundamental one in
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Asynchronous Transaction Scheduling
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Discovery Port Reset Chapter 15: US
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15.8.2 Port State and Control Chapt
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Data Toggle Chapter 15: USB Host, D
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Table 15‐6: Variable Length Trans
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Control Endpoint Operation Model Se
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Table 15‐9: Control Endpoint Bus
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Active = 0 Halted = 0 Transaction E
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Low‐Frequency Interrupts Chapter
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X-Ref Target - Figure 15-16 Operati
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Table 15‐19: iTD Transaction Stat
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Table 15‐22: iTD Buffer Pointer P
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15.10.9 siTD Endpoint Capabilities/
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15.10.12 siTD Back Link Pointer Cha
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15.10.15 Alternate Next qTD Pointer
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7:0 (cont’d) 15.10.17 qTD Buffer
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15.10.19 Queue Head Horizontal Link
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Table 15‐36: Endpoint Capabilitie
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Table 15‐38: Host‐Controller Ru
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15.10.24 FSTN Back Path Link Pointe
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X-Ref Target - Figure 15-24 Endpoin
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Gigabit Ethernet Controller 16.1 In
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Chapter 16: Gigabit Ethernet Contro
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Table 16‐2: Rx Buffer Descriptor
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Table 16‐3: Tx Buffer Descriptor
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X-Ref Target - Figure 16-3 Gigabit
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Counter Value to the PL Chapter 16:
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X-Ref Target - Figure 16-4 To creat
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Table 16‐6: Ethernet Control Regi
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16.5 Signals and I/O Connections 16
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Table 16‐8: Ethernet RGMII Interf
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SPI Controller 17.1 Introduction Ch
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17.2 Functional Description 17.2.1
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17.2.4 Slave Mode Chapter 17: SPI C
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Table 17‐1: SPI MIO Pins and EMIO
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18.1.2 System Viewpoint The system
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18.2 Functional Description Chapter
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Normal Mode Chapter 18: CAN Control
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Table 18‐3: CAN Message Word Regi
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Chapter 18: CAN Controller When arb
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X-Ref Target - Figure 18-4 Table 18
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Chapter 18: CAN Controller If any o
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d. Zero-out extended frame bits, [A
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tBIT_RATE = tSYNC_SEGMENT + tTIME_S
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Chapter 18: CAN Controller 3. Wait
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5. Determine if more messages are i
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Chapter 18: CAN Controller 1. Confi
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18.5.2 MIO‐EMIO Signals Chapter 1
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° 1, 1.5, or 2 stop bits Chapter 1
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19.2.3 Transmitter Data Stream Chap
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19.2.6 Mode Switch X-Ref Target - F
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4. Configure Baud Rate Generator (s
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Chapter 19: UART Controller 4. Repe
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Non‐FIFO Interrupts Chapter 19: U
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19.4 System Functions 19.4.1 Clocks
Page 467 and 468: Table 19‐4: UART MIO Pins and EMI
Page 469 and 470: ° Supports TO interrupt flag to av
Page 471 and 472: Chapter 20: I2C Controller data is
Page 473 and 474: Chapter 20: I2C Controller At the s
Page 475 and 476: 20.3 Register Overview An overview
Page 477 and 478: Chapter 21: Programmable Logic Desc
Page 481 and 482: Error Detection and Correction Chap
Page 487 and 488: 21.3 PS‐PL Interfaces Chapter 21:
Page 489 and 490: Power Chapter 22: Programmable Logi
Page 491 and 492: Chapter 22: Programmable Logic Desi
Page 497 and 498: X-Ref Target - Figure 22-1 MIO Pins
Page 499 and 500: X-Ref Target - Figure 22-3 MIO Pins
Page 505 and 506: 23.1.2 Block Diagram A block diagra
Page 507 and 508: Chapter 23: Programmable Logic (PL)
Page 509 and 510: X-Ref Target - Figure 23-5 PL Activ
Page 511 and 512: Table 23‐5: Cycle Count Packet Fo
Page 513 and 514: 23.4 Register Overview Table 23‐1
Page 515 and 516: 24.2 Voltage Domains Figure 24-1 sh
Page 517: Clocks 25.1 Introduction Chapter 25
Page 521 and 522: 25.3 CPU Clock Domains X-Ref Target
Page 523 and 524: Table 25‐2: PS Peripheral Clock C
Page 525 and 526: X-Ref Target - Figure 25-4 These fe
Page 527 and 528: 25.7 I/O Peripheral (IOP) Clocks I/
Page 529 and 530: Chapter 25: Clocks the RGMII interf
Page 531 and 532: X-Ref Target - Figure 25-10 IO PLL
Page 533 and 534: 25.12 Programming Model 25.12.1 Bra
Page 535 and 536: Table 25‐5: PLL Frequency Control
Page 537 and 538: Chapter 25: Clocks Zynq‐7000 EPP
Page 539 and 540: X-Ref Target - Figure 26-1 PS_POR_B
Page 541 and 542: X-Ref Target - Figure 26-3 System R
Page 543 and 544: Chapter 26: Reset System The PS doe
Page 545 and 546: Chapter 26: Reset System The first
Page 547 and 548: X-Ref Target - Figure 27-1 Chapter
Page 549 and 550: 27.2 Functional Description Chapter
Page 551 and 552: Chapter 27: JTAG and DAP Subsystem
Page 553 and 554: Chapter 27: JTAG and DAP Subsystem
Page 555 and 556: 27.6 Trace Port Interface Unit (TPI
Page 557 and 558: System Test and Debug 28.1 Introduc
Page 559 and 560: • Trace source: PTM, FTM, ITM •
Page 561 and 562: Table 28‐1: CTI Trigger Inputs an
Page 563 and 564: 28.2.6 Embedded Trace Buffer (ETB)
Page 565 and 566: 28.4 Register Overview 28.4.1 Memor
Page 567 and 568: Table 28‐6: CoreSight Component R
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28.5 Programming Model 28.5.1 Authe
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On‐Chip Memory (OCM) 29.1 Introdu
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• TrustZone support for on-chip R
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X-Ref Target - Figure 29-3 Arbitrat
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OCM Relocation Chapter 29: On‐Chi
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29.2.5 Interrupts Chapter 29: On‐
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Chapter 29: On‐Chip Memory (OCM)
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30.1.1 Block Diagram Figure 30-1 sh
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Chapter 30: Analog‐to‐Digital C
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30.5 Programming Model Chapter 30:
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31.2 Block Diagram X-Ref Target - F
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Device Secure Boot 32.1 Introductio
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X-Ref Target - Figure 32-3 BootROM
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32.2.8 Key Management Chapter 32: D
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Chapter 32: Device Secure Boot resu
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A.2 Solution Centers Appendix A: Ad
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ChipScope Pro Software and Cores Us
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Register Details B.1 Overview Appen
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B.3 Module Summary Module Name Modu
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Module Name Module Type Base Addres
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Register Name Address Width Type Re
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Register (AFI) AFI_RDCHAN_ISSUINGCA
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Absolute Address afi0: 0xF8008010 a
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Field Name Bits Type Reset Value De
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Register (AFI) AFI_WRDATAFIFO_LEVEL
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B.5 CAN Controller (can) Module Nam
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Register SRR Details Appendix B: Re
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Please refer to the CAN chapter for
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ETXFWMEMP (IXR_TXFWMEMP) ERXFWMFLL
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Page 639 and 640:
CTXFWMEMP (IXR_TXFWMEMP) CRXFWMFLL
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Description Watermark Interrupt Reg
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Register (can) TXFIFO_DLC Name TXFI
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Register TXHPB_DLC Details Field Na
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IDH (IDR_ID1) SRRRTR (IDR_SRR) IDE
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Register RXFIFO_DATA1 Details Field
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Register AFMR2 Details Field Name B
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Register AFMR4 Details Field Name B
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Register (ddrc) DRAM_param_reg0 Nam
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Reset Value 0x83015904 Description
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Description DRAM EMR, MR access Reg
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Register phy_cmd_timeout_rddata_cpt
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Register (ddrc) DLL_calib Name DLL_
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Name ctrl_reg4 Register (ddrc) ctrl
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Name ctrl_reg6 Register (ddrc) ctrl
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Register (ddrc) CHE_T_ZQ_Short_Inte
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Width 2 bits Access Type rw Reset V
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Register CHE_UNCORR_ECC_LOG_REG_OFF
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Register CHE_UNCORR_ECC_DATA_71_64_
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Register CHE_ECC_CORR_BIT_MASK_31_0
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Name Address PHY_Config0 0xf8006118
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Name Address phy_rd_dqs_cfg0 0xf800
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Register phy_we_cfg0 to phy_we_cfg3
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Register reg6c_6d2 to reg6c_6d3 Det
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Register dll_lock_sts Details Field
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Name axi_id Register (ddrc) axi_id
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Register (ddrc) axi_priority_rd_por
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Register excl_access_cfg0 to excl_a
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Register lpddr_ctrl2 Details Field
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Register (ddrc) phy_gate_lvl_fsm Na
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Register (cti) CTIINTACK Name CTIIN
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Absolute Address debug_cpu_cti0: 0x
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Register (cti) CTIINEN2 Name CTIINE
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Register (cti) CTIINEN5 Name CTIINE
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Register (cti) CTIOUTEN0 Name CTIOU
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Description ITTRIGIN Register Regis
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Width 32 bits Access Type wo Reset
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Register (cti) DEVID Name DEVID Rel
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Relative Address 0x00000FD8 Absolut
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Width 8 bits Access Type ro Reset V
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Register (cortexa9_pmu) PMXEVCNTR0
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Register (cortexa9_pmu) PMXEVCNTR5
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Register (cortexa9_pmu) PMXEVTYPER3
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Register (cortexa9_pmu) PMINTENSET
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Register (cortexa9_pmu) PMUSERENR N
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Register (ptm) ETMTSSCR Name ETMTSS
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Register (ptm) ETMACVR2 Name ETMACV
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Register (ptm) ETMACVR7 Name ETMACV
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Register ETMACTR2 Details Field Nam
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Width 18 bits Access Type mixed Res
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Register (ptm) ETMCNTVR2 Name ETMCN
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Register ETMSQ23EVR Details Field N
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Register ETMSQ13EVR Details Field N
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Access Type rw Reset Value 0x000000
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Access Type ro Reset Value 0x00C019
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Register ITMISCOUT Details Field Na
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Register ITATBCTR2 Details Field Na
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Register CTSR Details Field Name Bi
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Register LSR Details Field Name Bit
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Register DTIR Details Field Name Bi
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Access Type ro Reset Value 0x000000
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Register (ptm) COMPID1 Name COMPID1
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B.10 Debug Access Port (dap) Module
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Width 32 bits Access Type ro Reset
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Reset Value 0x0000B003 Description
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Register ROMENTRY15 Details Field N
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Register PERIPHID0 Details Field Na
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Description Component ID1 Register
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Register RRD Details Field Name Bit
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Register CTL Details Field Name Bit
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Page 857 and 858:
Page 859 and 860:
Name CTSR Register (etb) CTSR Relat
Page 861 and 862:
Page 863 and 864:
Page 865 and 866:
Page 867 and 868:
Register COMPID2 Details Field Name
Page 869 and 870:
Page 871 and 872:
Page 873 and 874:
Register FTMP2FDBG3 Details Field N
Page 875 and 876:
Description AXI Cycle Count clock p
Page 877 and 878:
Register FTMITTRIGOUTACK Details Fi
Page 879 and 880:
Absolute Address 0xF880BEF0 Width 2
Page 881 and 882:
Register CLAIMTAGSET Details Field
Page 883 and 884:
Absolute Address 0xF880BFC8 Width 1
Page 885 and 886:
Relative Address 0x00000FDC Absolut
Page 887 and 888:
Register (ftm) FTMCOMPONID0 Name FT
Page 889 and 890:
B.13 CoreSight Trace Funnel (funnel
Page 891 and 892:
Page 893 and 894:
Register ITATBCTR2 Details Field Na
Page 895 and 896:
Register CTSR Details Field Name Bi
Page 897 and 898:
Page 899 and 900:
Page 901 and 902:
Page 903 and 904:
Register COMPID2 Details Field Name
Page 905 and 906:
Page 907 and 908:
Register StimPort00 Details Field N
Page 909 and 910:
Page 911 and 912:
Page 913 and 914:
Page 915 and 916:
Page 917 and 918:
Page 919 and 920:
Page 921 and 922:
Page 923 and 924:
Page 925 and 926:
Page 927 and 928:
Page 929 and 930:
Page 931 and 932:
Page 933 and 934:
Page 935 and 936:
Page 937 and 938:
Page 939 and 940:
Absolute Address 0xF8805E20 Width 3
Page 941 and 942:
Description Integration Test Trigge
Page 943 and 944:
Description Integration Mode Contro
Page 945 and 946:
Relative Address 0x00000FB4 Absolut
Page 947 and 948:
Relative Address 0x00000FD0 Absolut
Page 949 and 950:
Absolute Address 0xF8805FE4 Width 8
Page 951 and 952:
Relative Address 0x00000FF8 Absolut
Page 953 and 954:
Page 955 and 956:
Reset Value 0x0000011F Description
Page 957 and 958:
Register (tpiu) CurrentTest Name Cu
Page 959 and 960:
Page 961 and 962:
Register ITTRFLINACK Details Field
Page 963 and 964:
Relative Address 0x00000EF8 Absolut
Page 965 and 966:
Description Lock Access Register Re
Page 967 and 968:
Page 969 and 970:
Page 971 and 972:
Register (tpiu) COMPID0 Name COMPID
Page 973 and 974:
B.16 Device Configuration Interface
Page 975 and 976:
Page 977 and 978:
Page 979 and 980:
Page 981 and 982:
Register LOCK Details Appendix B: R
Page 983 and 984:
Page 985 and 986:
Page 987 and 988:
Page 989 and 990:
Page 991 and 992:
Register (devcfg) ROM_SHADOW Name R
Page 993 and 994:
Register MCTRL Details Field Name B
Page 995 and 996:
Register XADCIF_INT_STS Details Fie
Page 997 and 998:
Register XADCIF_CMDFIFO Details Fie
Page 999 and 1000:
B.17 DMA Controller (dmac) Module N
Page 1001 and 1002:
Page 1003 and 1004:
Page 1005 and 1006:
Register DSR Details Field Name Bit
Page 1007 and 1008:
Page 1009 and 1010:
Absolute Address dmac0_ns: 0xF80040
Page 1011 and 1012:
Page 1013 and 1014:
Page 1015 and 1016:
Register FTR1 Details Field Name Bi
Page 1017 and 1018:
Page 1019 and 1020:
Page 1021 and 1022:
Page 1023 and 1024:
Page 1025 and 1026:
Page 1027 and 1028:
Page 1029 and 1030:
Page 1031 and 1032:
Page 1033 and 1034:
Page 1035 and 1036:
Page 1037 and 1038:
Page 1039 and 1040:
Page 1041 and 1042:
Page 1043 and 1044:
Page 1045 and 1046:
Description Channel PC for DMA chan
Page 1047 and 1048:
Relative Address 0x00000124 Absolut
Page 1049 and 1050:
Page 1051 and 1052:
Page 1053 and 1054:
Page 1055 and 1056:
Description Channel PC for DMA chan
Page 1057 and 1058:
Page 1059 and 1060:
Page 1061 and 1062:
Register LC0_0 Details Field Name B
Page 1063 and 1064:
Reset Value dmac0_ns: 0x00000000 dm
Page 1065 and 1066:
Page 1067 and 1068:
Page 1069 and 1070:
Page 1071 and 1072:
Page 1073 and 1074:
Page 1075 and 1076:
Page 1077 and 1078:
Page 1079 and 1080:
Page 1081 and 1082:
Page 1083 and 1084:
Page 1085 and 1086:
Page 1087 and 1088:
Page 1089 and 1090:
Page 1091 and 1092:
Page 1093 and 1094:
Page 1095 and 1096:
Page 1097 and 1098:
Page 1099 and 1100:
Page 1101 and 1102:
Page 1103 and 1104:
Page 1105 and 1106:
Page 1107 and 1108:
Page 1109 and 1110:
Page 1111 and 1112:
Access Type mixed Reset Value 0x000
Page 1113 and 1114:
Page 1115 and 1116:
Page 1117 and 1118:
Register CR3 Details Register (dmac
Page 1119 and 1120:
Page 1121 and 1122:
Page 1123 and 1124:
Register pcell_id_0 Details Field N
Page 1125 and 1126:
B.18 Gigabit Ethernet Controller (G
Page 1127 and 1128:
Page 1129 and 1130:
Page 1131 and 1132:
Name net_cfg Register (GEM) net_cfg
Page 1133 and 1134:
len_err_frame_disc (LENGTHERRDSCRD)
Page 1135 and 1136:
Page 1137 and 1138:
Page 1139 and 1140:
Name tx_status Register (GEM) tx_st
Page 1141 and 1142:
Register rx_qbar Details Appendix B
Page 1143 and 1144:
Register (GEM) intr_status Name int
Page 1145 and 1146:
Page 1147 and 1148:
Page 1149 and 1150:
Page 1151 and 1152:
Page 1153 and 1154:
Appendix B: Register Details operat
Page 1155 and 1156:
Name hash_top Register (GEM) hash_t
Page 1157 and 1158:
Register (GEM) spec_addr2_top Name
Page 1159 and 1160:
Register (GEM) spec_addr4_top Name
Page 1161 and 1162:
Page 1163 and 1164:
Register ipg_stretch Details Field
Page 1165 and 1166:
Register (GEM) spec_addr1_mask_top
Page 1167 and 1168:
Register octets_tx_top Details Appe
Page 1169 and 1170:
Register multi_frames_tx Details Ap
Page 1171 and 1172:
Register (GEM) frames_128to255b_tx
Page 1173 and 1174:
Description Frame Tx, 1024 to 1518-
Page 1175 and 1176:
Register multi_collisn_frames Detai
Page 1177 and 1178:
Description Deferred Transmission F
Page 1179 and 1180:
Register (GEM) octets_rx_top Name o
Page 1181 and 1182:
Register (GEM) multi_frames_rx Name
Page 1183 and 1184:
Page 1185 and 1186:
Page 1187 and 1188:
Name jab_rx Register (GEM) jab_rx S
Page 1189 and 1190:
Software Name XEMACPS_RXSYMBCNT Rel
Page 1191 and 1192:
Absolute Address gem0: 0xE000B1A4 g
Page 1193 and 1194:
Register udp_csum_errors Details Fi
Page 1195 and 1196:
Register timer_ns Details Field Nam
Page 1197 and 1198:
Name ptp_tx_ns Register (GEM) ptp_t
Page 1199 and 1200:
Page 1201 and 1202:
Register ptp_peer_rx_ns Details Fie
Page 1203 and 1204:
Page 1205 and 1206:
B.19 General Purpose I/O (gpio) Mod
Page 1207 and 1208:
Page 1209 and 1210:
Page 1211 and 1212:
Page 1213 and 1214:
Page 1215 and 1216:
Register (gpio) DATA_2_RO Name DATA
Page 1217 and 1218:
Page 1219 and 1220:
Software Name INTSTS Relative Addre
Page 1221 and 1222:
Description Interrupt Any Edge Sens
Page 1223 and 1224:
Page 1225 and 1226:
Absolute Address 0xE000A264 Width 2
Page 1227 and 1228:
Page 1229 and 1230:
Absolute Address 0xE000A2A4 Width 3
Page 1231 and 1232:
Page 1233 and 1234:
Absolute Address 0xE000A2E4 Width 3
Page 1235 and 1236:
Absolute Address gpv_qos301_cpu: 0x
Page 1237 and 1238:
Name aw_p Register (qos301) aw_p Re
Page 1239 and 1240:
Page 1241 and 1242:
Register (nic301_addr_region_ctrl_r
Page 1243 and 1244:
Page 1245 and 1246:
Page 1247 and 1248:
Page 1249 and 1250:
Width 16 bits Access Type ro Reset
Page 1251 and 1252:
TO (IXR_TO) Field Name Bits Type Re
Page 1253 and 1254:
B.23 L2 Cache (L2Cpl310) Module Nam
Page 1255 and 1256:
Page 1257 and 1258:
Page 1259 and 1260:
Page 1261 and 1262:
Page 1263 and 1264:
Page 1265 and 1266:
Register reg1_tag_ram_control Detai
Page 1267 and 1268:
Page 1269 and 1270:
Page 1271 and 1272:
Register reg2_int_mask Details Regi
Page 1273 and 1274:
Register reg2_int_raw_status Detail
Page 1275 and 1276:
Page 1277 and 1278:
Page 1279 and 1280:
Register (L2Cpl310) reg9_d_lockdown
Page 1281 and 1282:
Register (L2Cpl310) reg9_d_lockdown
Page 1283 and 1284:
Register reg9_d_lockdown4 Details F
Page 1285 and 1286:
Page 1287 and 1288:
Register reg9_unlock_way Details Fi
Page 1289 and 1290:
Page 1291 and 1292:
Register (L2Cpl310) reg15_power_ctr
Page 1293 and 1294:
Page 1295 and 1296:
Page 1297 and 1298:
Page 1299 and 1300:
Page 1301 and 1302:
Description SCU Invalidate All Regi
Page 1303 and 1304:
Page 1305 and 1306:
Register ICCICR Details Field Name
Page 1307 and 1308:
Register ICCIAR Details Field Name
Page 1309 and 1310:
Absolute Address 0xF8F0011C Width 3
Page 1311 and 1312:
Register (mpcore) Global_Timer_Cont
Page 1313 and 1314:
Absolute Address 0xF8F00210 Width 3
Page 1315 and 1316:
Register (mpcore) Private_Timer_Cou
Page 1317 and 1318:
Page 1319 and 1320:
Register Watchdog_Counter_Register
Page 1321 and 1322:
Register (mpcore) Watchdog_Interrup
Page 1323 and 1324:
Register Watchdog_Disable_Register
Page 1325 and 1326:
Register ICDICTR Details Field Name
Page 1327 and 1328:
Register ICDISR0 to ICDISR2 Details
Page 1329 and 1330:
Reset Value 0x0000FFFF Description
Page 1331 and 1332:
Register ICDISPR0 to ICDISPR2 Detai
Page 1333 and 1334:
Appendix B: Register Details Note:
Page 1335 and 1336:
Name Address ICDIPTR22 0xf8f01858 I
Page 1337 and 1338:
Description Interrupt Configuration
Page 1339 and 1340:
Register ppi_status Details Field N
Page 1341 and 1342:
Register ICDSGIR Details Field Name
Page 1343 and 1344:
Page 1345 and 1346:
Register ICPIDR3 Details Field Name
Page 1347 and 1348:
B.25 On‐Chip Memory (ocm) Module
Page 1349 and 1350:
Page 1351 and 1352:
B.26 Quad‐SPI Flash Controller (q
Page 1353 and 1354:
leg_flsh (IFMODE) Register Config_r
Page 1355 and 1356:
Register Intr_status_REG Details Fi
Page 1357 and 1358:
Register Intrpt_dis_REG Details Fie
Page 1359 and 1360:
Register En_REG Details Field Name
Page 1361 and 1362:
Page 1363 and 1364:
Register LPBK_DLY_ADJ Details Appen
Page 1365 and 1366:
Absolute Address 0xE000D0A0 Width 3
Page 1367 and 1368:
Page 1369 and 1370:
B.27 SD Controller (sdio) Module Na
Page 1371 and 1372:
Page 1373 and 1374:
Register Block_Size_Block_Count Det
Page 1375 and 1376:
Register (sdio) Transfer_Mode_Comma
Page 1377 and 1378:
Page 1379 and 1380:
Register Present_State Details Fiel
Page 1381 and 1382:
Page 1383 and 1384:
Description Host control register P
Page 1385 and 1386:
Page 1387 and 1388:
Absolute Address sd0: 0xE010002C sd
Page 1389 and 1390:
Page 1391 and 1392:
Page 1393 and 1394:
Page 1395 and 1396:
Page 1397 and 1398:
Page 1399 and 1400:
Page 1401 and 1402:
Register Capabilities Details Field
Page 1403 and 1404:
Page 1405 and 1406:
Page 1407 and 1408:
Register ADMA_system_address Detail
Page 1409 and 1410:
Register SPI_interrupt_support Deta
Page 1411 and 1412:
B.28 System Level Control Registers
Page 1413 and 1414:
Page 1415 and 1416:
Page 1417 and 1418:
Register SLCR_LOCK Details Field Na
Page 1419 and 1420:
Page 1421 and 1422:
Page 1423 and 1424:
Register (slcr) DDR_PLL_CFG Name DD
Page 1425 and 1426:
Page 1427 and 1428:
Page 1429 and 1430:
Description USB 1 ULPI Clock Contro
Page 1431 and 1432:
Page 1433 and 1434:
Page 1435 and 1436:
Register SPI_CLK_CTRL Details Field
Page 1437 and 1438:
Page 1439 and 1440:
Register TOPSW_CLK_CTRL Details Fie
Page 1441 and 1442:
Register FPGA2_CLK_CTRL Details Fie
Page 1443 and 1444:
Register PSS_RST_CTRL Details Field
Page 1445 and 1446:
Register USB_RST_CTRL Details Field
Page 1447 and 1448:
Register SDIO_RST_CTRL Details Fiel
Page 1449 and 1450:
Register CAN_RST_CTRL Details Field
Page 1451 and 1452:
Page 1453 and 1454:
Page 1455 and 1456:
Page 1457 and 1458:
Width 32 bits Access Type rw Reset
Page 1459 and 1460:
Page 1461 and 1462:
Page 1463 and 1464:
Register DDR_CAL_START Details Fiel
Page 1465 and 1466:
Register (slcr) DDR_URGENT_SEL Name
Page 1467 and 1468:
Page 1469 and 1470:
Page 1471 and 1472:
Page 1473 and 1474:
Page 1475 and 1476:
Page 1477 and 1478:
Page 1479 and 1480:
Page 1481 and 1482:
Page 1483 and 1484:
Register MIO_PIN_14 Details Field N
Page 1485 and 1486:
Page 1487 and 1488:
Page 1489 and 1490:
Page 1491 and 1492:
Page 1493 and 1494:
Page 1495 and 1496:
Page 1497 and 1498:
Page 1499 and 1500:
Page 1501 and 1502:
Page 1503 and 1504:
Page 1505 and 1506:
Page 1507 and 1508:
Page 1509 and 1510:
Page 1511 and 1512:
Relative Address 0x000007A8 Absolut
Page 1513 and 1514:
Register (slcr) MIO_PIN_44 Name MIO
Page 1515 and 1516:
Page 1517 and 1518:
Page 1519 and 1520:
Page 1521 and 1522:
Page 1523 and 1524:
Register (slcr) MIO_FMIO_GEM_SEL Na
Page 1525 and 1526:
Page 1527 and 1528:
Register (slcr) SD0_WP_CD_SEL Name
Page 1529 and 1530:
Absolute Address 0xF8000910 Width 3
Page 1531 and 1532:
Register (slcr) GPIOB_CFG_CMOS25 Na
Page 1533 and 1534:
Page 1535 and 1536:
Page 1537 and 1538:
Page 1539 and 1540:
Page 1541 and 1542:
Page 1543 and 1544:
Register (slcr) DDRIOB_DRIVE_SLEW_D
Page 1545 and 1546:
Register DDRIOB_DDR_CTRL Details Fi
Page 1547 and 1548:
Register DDRIOB_DCI_STATUS Details
Page 1549 and 1550:
Page 1551 and 1552:
int_en0 (INT_EN0) state (STATE) Fie
Page 1553 and 1554:
Register (pl353) memc_cfg_clr Name
Page 1555 and 1556:
Set_t6 (SET_T6) Set_t5 (SET_T5) Set
Page 1557 and 1558:
Page 1559 and 1560:
Page 1561 and 1562:
eserved 2 ro 0x0 Reserved. Do not m
Page 1563 and 1564:
Reset Value 0x0024ABCC Description
Page 1565 and 1566:
Register user_config Details Regist
Page 1567 and 1568:
Page 1569 and 1570:
Page 1571 and 1572:
Register (pl353) ecc_addr0_1 Name e
Page 1573 and 1574:
Register ecc_value1_1 Details Field
Page 1575 and 1576:
Register ecc_value3_1 Details Field
Page 1577 and 1578:
Absolute Address spi0: 0xE0006000 s
Page 1579 and 1580:
Register Intr_status_reg0 Details F
Page 1581 and 1582:
Page 1583 and 1584:
Register (SPI) En_reg0 Name En_reg0
Page 1585 and 1586:
Page 1587 and 1588:
Page 1589 and 1590:
Page 1591 and 1592:
Page 1593 and 1594:
Page 1595 and 1596:
Register (ttc) Clock_Control_3 Name
Page 1597 and 1598:
Register Counter_Control_2 Details
Page 1599 and 1600:
Value (MASK) Register Counter_Value
Page 1601 and 1602:
Absolute Address ttc0: 0xF800102C t
Page 1603 and 1604:
Description Match value Match (MATC
Page 1605 and 1606:
Match (MATCH) Register Match_3_Coun
Page 1607 and 1608:
Register (ttc) Interrupt_Register_3
Page 1609 and 1610:
Register Interrupt_Enable_3 Details
Page 1611 and 1612:
Absolute Address ttc0: 0xF8001078 t
Page 1613 and 1614:
B.33 UART Controller (UART) Module
Page 1615 and 1616:
TXRES (TXRST) RXRES (RXRST) Field N
Page 1617 and 1618:
Page 1619 and 1620:
Register Intrpt_mask_reg0 Details F
Page 1621 and 1622:
Page 1623 and 1624:
Page 1625 and 1626:
Page 1627 and 1628:
Page 1629 and 1630:
B.34 USB Controller (usb) Module Na
Page 1631 and 1632:
Page 1633 and 1634:
Page 1635 and 1636:
Page 1637 and 1638:
Register (usb) HWTXBUF Name HWTXBUF
Page 1639 and 1640:
Page 1641 and 1642:
Page 1643 and 1644:
Register HCSPARAMS Details Field Na
Page 1645 and 1646:
Page 1647 and 1648:
Register USBCMD Details Field Name
Page 1649 and 1650:
Page 1651 and 1652:
HCH (IXR_HCH) Appendix B: Register
Page 1653 and 1654:
Absolute Address usb0: 0xE0002148 u
Page 1655 and 1656:
UEE (IXR_UE) UE (IXR_UI) Field Name
Page 1657 and 1658:
Register PERIODICLISTBASE_DEVICEADD
Page 1659 and 1660:
Register TTCTRL Details Field Name
Page 1661 and 1662:
Register TXFILLTUNING Details Field
Page 1663 and 1664:
Register IC_USB Details Field Name
Page 1665 and 1666:
Page 1667 and 1668:
Absolute Address usb0: 0xE0002178 u
Page 1669 and 1670:
Register (usb) PORTSC1 Name PORTSC1
Page 1671 and 1672:
Page 1673 and 1674:
Page 1675 and 1676:
Page 1677 and 1678:
Page 1679 and 1680:
Register USBMODE Details Field Name
Page 1681 and 1682:
Register ENDPTSETUPSTAT Details Fie
Page 1683 and 1684:
Register (usb) ENDPTFLUSH Name ENDP
Page 1685 and 1686:
Register ENDPTSTAT Details Field Na
Page 1687 and 1688:
Register (usb) ENDPTCTRL0 Name ENDP
Page 1689 and 1690:
Register ENDPTCTRL1 to ENDPTCTRL12
Page 1691:
Access Type Description w1crs w: 1/
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