ug585-Zynq-7000-TRM

Register StimPort30 Details
Field Name Bits Type Reset Value Description
Register (itm) StimPort31
Name StimPort31
Relative Address 0x0000007C
Absolute Address 0xF880507C
Width 32 bits
Access Type rw
Reset Value 0x00000000
Appendix B: Register Details
31:0 rw 0x0 Each of the 32 stimulus ports is represented by a
virtual address, creating 32 stimulus registers. A
write to one of these locations causes data to be
written into the FIFO if the corresponding bit in
the Trace Enable Register is set and ITM is
enabled. Reading from any of the stimulus ports
returns the FIFO status (notFull(1) / Full(0)) only
if the ITM is enabled. This enables more efficient
core register allocation because the stimulus
address has already been generated.
The ITM transmits SWIT packets using leading
zero compression. Packets can be 8, 16, or 32 bits.
The bank of 32 registers is split into a low-16 (0 to
15) and a high-16 (16 to 31). Writes to the high-16
are discarded by the ITM whenever secure
non-invasive trace is disabled, regardless of how
the Trace Enable Register bits [31:16] are set. Both
the high-16 and
low-16 are be disabled when non-invasive trace is
disabled. When an input is disabled it must not
alter the interface response and must always
return an OK without stalling.
Description Stimulus Port Register 31
Zynq‐7000 EPP Technical Reference Manual www.xilinx.com 931
UG585 (v1.2) August 8, 2012