A Slew Rate Controlled Output Driver Using PLL as ... - Imec

A Slew Rate Controlled Output Driver
Using PLL as Compensation Circuit
Soon-Kyun Soon Kyun Shin, Seok-Min Seok Min Jung, Jin-Ho Jin Ho Seo,
Myeong-Lyong
Myeong Lyong Ko and Jae-Whui Jae Whui Kim
SAMSUNG Electronics

✙ Overview
Outline
✙ Introduction to Slew Rate Control
✙ Circuits for Compensation & Slew Rate Control
✙ Simulation & Test Results
✙ Conclusions
24 September 2002 -2/18 -
ESSCIRC 2002 , Soon-Kyun Shin

✙ Applications
ATA Mode
Overview of ATA/ATAPI
HDD, DVD-ROM, CD-ROM,CD-RW
IEEE1394 to ATAPI Bridge Chip
USB2.0 to ATAPI Bridge Chip
Data Rate
(Signal Frequency)
Slew Rate Specification
@Load Condition
33 MBps
UDMA33 Min tr,tf 5ns@40pF
(8.25MHz)
66 MBps
UDMA66 Max 1.25[V/ns]@40pF
(16.5MHz)
100 MBps
UDMA100 0.4 ~ 1.0[V/ns]@15~40pF
(25MHz)
133 MBps
UDMA133 0.4 ~ 1.0[V/ns]@15~40pF
(33.3MHz)
Cable Type
40 conductor
80 conductor
80 conductor
80 conductor
24 September 2002 -3/18 -
ESSCIRC 2002 , Soon-Kyun Shin

Key issues
✙ Slew Rate : 0.4 ~ 1.0 [V/ns] @15~40pF
Must guarantee within 2.5 times variation over PVT (
Process, Voltage, Temperature) variation.
Load variation is 2.67 times variation compared to15pF.
Slew rate is too fast to use feedback architecture.
External resistor is not allowed.
⇒ PVT compensation circuit is needed.
⇒ Compensation for load variation is needed.
24 September 2002 -4/18 -
ESSCIRC 2002 , Soon-Kyun Shin

Voltage
Voltage
PAD
pMOS driver
Gate voltage
Concept of Slew Rate Control
Interval time
15pF Load
First step
Interval time
First step
15pF Load
Second step
nMOS driver
Gate voltage
40pF Load
40pF Load
Second step
PAD
time
time
✙ The second step of gate
voltage does not affect the
slew rate of small load
capacitance.
✙ The interval time can be
estimated through simulation
of first voltage step over PVT
variation.
24 September 2002 -5/18 -
ESSCIRC 2002 , Soon-Kyun Shin

TRI-STATE
DATA
FIN
Simplified Block Diagram
Phase
Frequency
Detector
Tri-state
Control
Logic
UP
DOWN
PC
NC
Slew Rate
Control Block
Divider
(1/N)
Voltage
Controlled
Oscillator
24 September 2002 -6/18 -
ESSCIRC 2002 , Soon-Kyun Shin
VCON
PG
NG
FOUT
Tolerant & Failsafe
pMOS Driver
Tolerant & Failsafe
nMOS Driver
VPBIAS
VNBIAS
PAD

VCON
Voltage Controlled Oscillator
Id
Ctot
N : the Number of delay stage
VDD
VPBIAS
FOUT
VNBIAS
24 September 2002 -7/18 -
ESSCIRC 2002 , Soon-Kyun Shin
f
osc
1
= =
N( t1+ t2) N
I d
CV
tot DD
fosc : oscillation frequency of VCO
t1, t2 : charge and discharge time
N : number of delay stage
Ctot : total capacitance of each stage
Vdd : supply voltage
Id : bias current

Characteristics of PLL
✙ PLL’s characteristics in locked condition
Constant frequency is generated over PVT
corners.
✙ Constant frequency means that the delay time is
constant in each delay stage of VCO over PVT
variation.
The replica of VCO’s delay stage is used in
output driver’s slew rate control block.
24 September 2002 -8/18 -
ESSCIRC 2002 , Soon-Kyun Shin

TRI-STATE
DATA
FIN
Simplified Block Diagram
Phase
Frequency
Detector
Tri-state
Control
Logic
UP
DOWN
PC
NC
Slew Rate
Control Block
Divider
(1/N)
Voltage
Controlled
Oscillator
24 September 2002 -9/18 -
ESSCIRC 2002 , Soon-Kyun Shin
VCON
PG
NG
FOUT
Tolerant & Failsafe
pMOS Driver
Tolerant & Failsafe
nMOS Driver
VPBIAS
VNBIAS
PAD

PC
NC
Control of Gate Voltage
First
pull down
First
pull up
Constant Delay Stage
Constant Delay Stage
Second
pull down
Second
pull up
24 September 2002 - 10/18 -
ESSCIRC 2002 , Soon-Kyun Shin
PG
NG
PAD

VPBIAS
PC
NC
VNBIAS
Replica of
VCO
Slew Rate Control Circuit
Icontrol
N3 N4
N1 N2
P1 P2
P3 P4
Icontrol
PG
NG
VBIAS
N1, P1 have the same length and different
width of VCO’s biasing MOS.
Therefore, they act like current mirrors.
PAD
I I
K K N
= × =
control d
CV
f
tot DD
Icontrol : sinking and sourcing current to the
gate of driver MOS.
K : the ratio factor of current mirror
Fosc : oscillation frequency of VCO
N : the number of delay stage
Ctot : total capacitance of each stage
Vdd : the supply voltage
Id : the bias current of VCO
24 September 2002 - 11/18 -
ESSCIRC 2002 , Soon-Kyun Shin
osc

Slew Rate Control
✙ Constant delay is generated and used in slew rate
control circuit for load variation.
The replica of VCO’s delay stage is used in
output driver’s slew rate control block.
✙ Current source is used to reduce slew rate
variation over PVT variations.
The same length of MOS in VCO’s delay
stage is used in output driver’s slew rate
control block.
24 September 2002 - 12/18 -
ESSCIRC 2002 , Soon-Kyun Shin

Simulation Results(3/3)
✙ Simulation results of slew rate
Slew Rate Simulation Results [V/ns]
Specification 0.4 ~ 1.0
Conventional output driver 0.305 ~ 1.216
Proposed output driver 0.403 ~ 0.986
24 September 2002 - 15/18 -
ESSCIRC 2002 , Soon-Kyun Shin

Layout of Test Chip
PLL
✙ Process : 0.18um 1-poly, 6-metal CMOS technology
✙ Output driver : 70[um] X 401[um]
Bias Voltage
Slew Rate Controlled Output Drivers
✙ PLL : 421[um] X 317[um]
24 September 2002 - 16/18 -
ESSCIRC 2002 , Soon-Kyun Shin

15pF
Measured Results
40pF
24 September 2002 - 17/18 -
ESSCIRC 2002 , Soon-Kyun Shin

Conclusions
✙ Compensation current is used to reduce the slew rate
variation over PVT corners.
✙ A constant delay time is generated to reduce the slew
rate variation over load variation using replica of VCO
in PLL.
✙ Implemented in 0.18um CMOS and satisfied the
UDMA100 specifications.
✙ Simulation results and test waveforms were shown.
✙ The slew rate variation over PVT and load variation is
reduced using PLL as compensation circuit.
24 September 2002 - 18/18 -
ESSCIRC 2002 , Soon-Kyun Shin