Backside Circuit Edit on Device Level - New Methodologies - Imec

TU Berlin - Germany 

Section Semiconductor Devices 

<strong>Backside</strong> <strong>Circuit</strong> <strong>Edit</strong> on Device Level - 

New Methodologies of Contacting <strong>Circuit</strong> Nodes 

Rudolf Schlangen 

Dr. Uwe Kerst 

Prof. Dr. Christian Boit 

Tu-Berlin, Semiconductor Devices 

Rajesh Jain 

Tahir Malik 

Dr. Ted Lundquist 

Credence DCG, USA 

02.10.2006 Rudolf Schlangen EFUG 1 

berlin

Motivation 

● New Packages and high Metal Stacks enforce <strong>Backside</strong> CE 

● Shrinking of IC Technology 

● Higher Device Density 

● <strong>Backside</strong> CE becomes more and more difficult 

● New Contacts offer new Solutions 


berlin

1 

2 

3 

Mechanical thinning to 10 - 40µm 

(locally or full die) 

FIB - trench to n-well 

(100 - 600 µm 2 ) 

FIB - trench to STI 

(4 - 50 µm 2 ) 

bulk Si 

n-well 

contrast 

7 µm STI 

150µm 

<strong>Backside</strong> CE Process 

NW 

W 

mechanically removed bulk Silicon 

FIB removed bulk Silicon 

Poly 

bulk-Si 


STI 

IMD 

M1 

2 

3 

berlin 

1 

Si 

PW

Output 

n-FET 

p-FET 

120nm Ring Oszillator 

Divider 

1/1024 

RO´s 

20µm 

bulk Si 

STI 

actives 

150µm 

150µm 

STI Opening 

Trenches 

STI Endpoint 

N-well 

Endpoint 


berlin

Output 

n-FET 

p-FET 

120nm Ring Oszillator 

Divider 

1/1024 

RO´s 

20µm 

bulk Si 

STI 

actives 


STI 

M1 

X - Section 

FIB - SiO 2 

350nm 

FET 

0.4µm 

berlin 

multiple oversized openings 

impact on max. frequency > 5%

W 

Different Ways to access a <strong>Circuit</strong> Node 

1 Targeting M1, M2, M3… 

2 Contact to Contact (CtC) 

3 Contact to Silicide (CtS) 

4 Contact to Poly Si 

2 3 

1 

NW PW 

p + n + 

p-Poly 

CoSi 

STI 

IMD 

M1 

FIB deposited Pt 

n-Poly 


4 

berlin

Vdd 

● direct contact to metal 

● access to M1, M2, M3, M4 

● only through STI area 

Conventional <strong>Backside</strong> CE 

access area blocked by: 

diffusion area, poly-Si, or lower metal layers 

p- MOS 

in 

Vdd 

out 

n- MOS 

metal 1 

metal 2 

diffusion 


GND 

berlin 

poly - gate 

n-well 

contact

● direct contact to metal 

● access to M1, M2, M3, M4 

Conventional <strong>Backside</strong> CE 

● only through STI area 

access area blocked by: 

diffusion area, poly-Si, or lower metal layers 

● requires high aspect ratio node access holes 

increased via resistance 

higher risk for circuitry / CE 


berlin

Vdd 

● direct contact to the metal (W) 

● reliable Endpoint 

● access to “every” signal 

● reduced via resistance 

p- MOS 

similar to every 

output in CMOS 

Contact to Contact 

in 

Vdd 

out 

n- MOS 

metal 1 

metal 2 



Si 

contacts 

0.4µm 

GND 

STI 

berlin 

poly - gate 

n-well 


● direct contact to the metal (W) 

● reliable Endpoint 

● access to “every” signal 

● reduced via resistance 

● at least 2 contacts necessary 

Pt 

STI 

350nm 

M1 

Contact to Contact 

sourcedrain 

drain source 

gate 

bulk-Si 

node M1 of interest 


berlin

Vdd 

p- MOS 

Contact to Silicide 

● contact to the CoSi Silicide 

(CoSi covers every diffusion / active) 

● possible without any Metal / Contact 

● modification on device level 

in 

Vdd 

out 

n- MOS 

ONLY 

with CtS 

metal 1 

metal 2 



GND 

berlin 

poly - gate 

n-well 


STI 

● cut using lowest Beam Current 

Endpoint on Silicide 

● monitoring the average brightness 

IMD 

FIB-Pt 

n + 

CoSi 

PW 

n-Poly 

time [s] 


brightness 

EPD Tool 

CoSi 

endpoint 

berlin

contact 

last picture of 

cut operation 


CtS Endpoint Window 


berlin

STI p-well 

0.5µm 

W contact 

M1 

FIB created 

Pt contact 

IMD source 

diff. area 

M2 


CoSi 

p-well 

n-diffusion 


Pt 

berlin

Vdd 

● always accessible through STI 

● low risk to device 

● reliable endpoint 

p- MOS 

Ct poly Si 

Contact to Poly Si 

in 

Vdd 

out 

n- MOS 

metal 1 

metal 2 



GND 

berlin 

poly - gate 

n-well 


poly Si IMD 

last picture of 

cut operation 

Endpoint to Poly Si 

Poly Si Endpoint Window 


berlin

output 

1 

2 

3 

4 

Inverter Chain 

Test on Azuma Chip 

input 

1 

2 

3 

4 

CtS 

1 

n-FET 

2 


3 

4 

berlin

output 

1 

2 

3 

4 



input 

1 

2 

3 

4 

CtS 

n-FET 


berlin

output 

1 

2 

3 

4 


CtS n-FET 

Ct poly Si 

cut 


input 

1 

2 

3 

4 


berlin 

Ct poly Si

output 

1 

2 

3 

4 


CtS n-FET 

Ct poly Si 

cut 


input 

1 

2 

3 

4 


berlin

output 

1 

2 

3 

4 


CtS n-FET 

Ct poly Si 

cut 


input 

1 

2 

3 

4 


berlin

output 

1 

2 

3 

4 


CtS p-FET 

CtS n-FET 

Ct poly Si 

cut 


input 

1 

2 

3 

4 

CtS 

p-FET 


berlin

output 

1 

2 

3 

4 


CtS p-FET 

CtS n-FET 

Ct poly Si 

cut 


input 

1 

2 

3 

4 


berlin

output 

1 

2 

3 

4 


CtS p-FET 

CtS n-FET 

Ct poly Si 

cut 


input 

1 

2 

3 

4 


berlin

Summary 

● Direct Contact to Contacts, Silicide & Poly presented 

● Ct Silicide covers every CMOS Output 

● Contact Properties sufficient for Probing and CE 

● Via aspect ratio is strongly decreased 

● Ct Poly covers every CMOS Input 

● Critical high aspect ratio holes only 

needed for cut operations 


Pt 

CoSi 

berlin 

p-well 

350 nm 

n-diff

Backside Circuit Edit on Device Level - New Methodologies - Imec

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?