Backside Circuit Edit on Device Level - New Methodologies - Imec

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Output n-FET p-FET 120nm Ring Oszillator Divider 1/1024 RO´s 20µm bulk Si STI actives 150µm 150µm STI Opening Trenches STI Endpoint N-well Endpoint 02.10.2006 Rudolf Schlangen EFUG 4 berlin
Output n-FET p-FET 120nm Ring Oszillator Divider 1/1024 RO´s 20µm bulk Si STI actives 02.10.2006 Rudolf Schlangen EFUG 5 STI M1 X - Secti<strong>on</strong> FIB - SiO 2 350nm FET 0.4µm berlin multiple oversized openings impact <strong>on</strong> max. frequency > 5%
Page 1 and 2: TU Berlin - Germany Section Semicon
Page 3: 1 2 3 Mechanical thinning to 10 - 4
Page 7 and 8: Vdd ● direct contact to metal ●
Page 9 and 10: Vdd ● direct contact to the metal
Page 11 and 12: Vdd p- MOS Contact to Silicide ●
Page 13 and 14: contact last picture of cut operati
Page 15 and 16: Vdd ● always accessible through S
Page 17 and 18: output 1 2 3 4 Inverter Chain Test
Page 19 and 20: output 1 2 3 4 Inverter Chain CtS n
Page 21 and 22: output 1 2 3 4 Inverter Chain CtS n
Page 23 and 24: output 1 2 3 4 Inverter Chain CtS p
Page 25: Summary ● Direct Contact to Conta

Backside Circuit Edit on Device Level - New Methodologies - Imec

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