Backside Circuit Edit on Device Level - New Methodologies - Imec
Backside Circuit Edit on Device Level - New Methodologies - Imec
Backside Circuit Edit on Device Level - New Methodologies - Imec
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Vdd<br />
● direct c<strong>on</strong>tact to the metal (W)<br />
● reliable Endpoint<br />
● access to “every” signal<br />
● reduced via resistance<br />
p- MOS<br />
similar to every<br />
output in CMOS<br />
C<strong>on</strong>tact to C<strong>on</strong>tact<br />
in<br />
Vdd<br />
out<br />
n- MOS<br />
metal 1<br />
metal 2<br />
diffusi<strong>on</strong><br />
02.10.2006 Rudolf Schlangen EFUG 9<br />
Si<br />
c<strong>on</strong>tacts<br />
0.4µm<br />
GND<br />
STI<br />
berlin<br />
poly - gate<br />
n-well<br />
c<strong>on</strong>tact
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