Backside Circuit Edit on Device Level - New Methodologies - Imec

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STI p-well 0.5µm W contact M1 FIB created Pt contact IMD source diff. area M2 Endpoint on Silicide CoSi p-well n-diffusion 02.10.2006 Rudolf Schlangen EFUG 14 Pt berlin
Vdd ● always accessible through STI ● low risk to device ● reliable endpoint p- MOS Ct poly Si Contact to Poly Si in Vdd out n- MOS metal 1 metal 2 diffusion 02.10.2006 Rudolf Schlangen EFUG 15 GND berlin poly - gate n-well contact
Page 1 and 2: TU Berlin - Germany Section Semicon
Page 3 and 4: 1 2 3 Mechanical thinning to 10 - 4
Page 5 and 6: Output n-FET p-FET 120nm Ring Oszil
Page 7 and 8: Vdd ● direct contact to metal ●
Page 9 and 10: Vdd ● direct contact to the metal
Page 11 and 12: Vdd p- MOS Contact to Silicide ●
Page 13: contact last picture of cut operati
Page 17 and 18: output 1 2 3 4 Inverter Chain Test
Page 19 and 20: output 1 2 3 4 Inverter Chain CtS n
Page 21 and 22: output 1 2 3 4 Inverter Chain CtS n
Page 23 and 24: output 1 2 3 4 Inverter Chain CtS p
Page 25: Summary ● Direct Contact to Conta

Backside Circuit Edit on Device Level - New Methodologies - Imec

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