Backside Circuit Edit on Device Level - New Methodologies - Imec

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output

1

2

3

4

Inverter Chain

CtS p-FET

CtS n-FET

Ct poly Si

cut

Test on Azuma Chip

input

1

2

3

4

CtS

p-FET

02.10.2006 Rudolf Schlangen EFUG 22

berlin

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output 1 2 3 4 Inverter Chain CtS p-FET CtS n-FET Ct poly Si cut Test on Azuma Chip input 1 2 3 4 CtS p-FET 02.10.2006 Rudolf Schlangen EFUG 22 berlin

output 1 2 3 4 Inverter Chain CtS p-FET CtS n-FET Ct poly Si cut Test on Azuma Chip input 1 2 3 4 02.10.2006 Rudolf Schlangen EFUG 23 berlin

Page 1 and 2: TU Berlin - Germany Section Semicon
Page 3 and 4: 1 2 3 Mechanical thinning to 10 - 4
Page 5 and 6: Output n-FET p-FET 120nm Ring Oszil
Page 7 and 8: Vdd ● direct contact to metal ●
Page 9 and 10: Vdd ● direct contact to the metal
Page 11 and 12: Vdd p- MOS Contact to Silicide ●
Page 13 and 14: contact last picture of cut operati
Page 15 and 16: Vdd ● always accessible through S
Page 17 and 18: output 1 2 3 4 Inverter Chain Test
Page 19 and 20: output 1 2 3 4 Inverter Chain CtS n
Page 21: output 1 2 3 4 Inverter Chain CtS n
Page 25: Summary ● Direct Contact to Conta

Backside Circuit Edit on Device Level - New Methodologies - Imec

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