Backside Circuit Edit on Device Level - New Methodologies - Imec

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● direct contact to metal ● access to M1, M2, M3, M4 Conventional <strong>Backside</strong> CE ● only through STI area access area blocked by: diffusion area, poly-Si, or lower metal layers ● requires high aspect ratio node access holes increased via resistance higher risk for circuitry / CE 02.10.2006 Rudolf Schlangen EFUG 8 berlin
Vdd ● direct contact to the metal (W) ● reliable Endpoint ● access to “every” signal ● reduced via resistance p- MOS similar to every output in CMOS Contact to Contact in Vdd out n- MOS metal 1 metal 2 diffusion 02.10.2006 Rudolf Schlangen EFUG 9 Si contacts 0.4µm GND STI berlin poly - gate n-well contact
Page 1 and 2: TU Berlin - Germany Section Semicon
Page 3 and 4: 1 2 3 Mechanical thinning to 10 - 4
Page 5 and 6: Output n-FET p-FET 120nm Ring Oszil
Page 7: Vdd ● direct contact to metal ●
Page 11 and 12: Vdd p- MOS Contact to Silicide ●
Page 13 and 14: contact last picture of cut operati
Page 15 and 16: Vdd ● always accessible through S
Page 17 and 18: output 1 2 3 4 Inverter Chain Test
Page 19 and 20: output 1 2 3 4 Inverter Chain CtS n
Page 21 and 22: output 1 2 3 4 Inverter Chain CtS n
Page 23 and 24: output 1 2 3 4 Inverter Chain CtS p
Page 25: Summary ● Direct Contact to Conta

Backside Circuit Edit on Device Level - New Methodologies - Imec

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