CMOS Production Compatible SiGe Heteroepitaxy for High ... - Imec

CMOS Production Compatible SiGe
Heteroepitaxy for High Frequency
Circuits
G.Ritter, D.Bolze, G.Fischer, D.Knoll, P.Schley, B.Tillack, D.Wolansky
1. Introduction
Institute for Semiconductor Physics,
Walter-Korsing-Straße 2, 15230 Frankfurt (Oder), Germany
A very critical processing step to integrate Si/SiGe HBTs is the
heteroepitaxy. For an HBT module designed for integration into
CMOS technology and to achieve cut-off frequencies of about 40
GHz, Low Pressure Chemical Vapor Deposition (LPCVD) has been
used as epitaxial technique. We demonstrate by statistical methods
that essential process capability indices of LPCVD epitaxy meet the
manufacturing requirements for high frequency devices. Furthermore,
we show that despite a relative high base Ge content the
transistor yield is not seriously limited by pipes.
The range of applications amenable to the well established Si CMOS
technology can be extended to high frequency applications by adding Si/SiGe
heterojunction bipolar transistors (HBTs). Very complex BICMOS processes
with integrated HBTs have been demonstrated (see for example 1-3) ). Recently
4)
, the stability and high volume production compatibility of UHV CVD epitaxy
for such technologies were demonstrated.
However, an essential trade-off is between performance and complexity, and
hence cost. Therefore, a main feature of our HBT module designed for post-
CMOS integration is its simplicity. Nevertheless, to achieve a sufficient device
performance with cut-off frequencies of about 40 GHz, the epitaxy had to be
carefully optimised. To this purpose, we used Low Pressure Chemical Vapor
Deposition 5) (LPCVD) as an epitaxial technique with potentially lower cost of
ownership than UHV CVD but not yet examined with respect to the
requirements of mass production. Therefore, the
aim of our paper is just to demonstrate the process capability of Rapid
Thermal LPCVD (RTCVD) heteroepitaxy for production of high frequency
devices.

Ge Content (%)
2. Experimental
The tested epitaxial layer stacks, consisting of Si-low doped collector, SiGe
base, and Si-low doped emitter, were in situ deposited on LOCOS structures
in a commercial single-wafer RTCVD reactor. A typical Ge profile is shown in
Fig. 1. Transistor parameters primarily influenced by the epitaxial
characteristic were measured. To obtain reliable statistics, about 300 similarly
processed 4“ wafers were studied. On each wafer, the parameters were
measured on 120 chips. As measure for the stability and wafer uniformity of
the epitaxial base doping, the pinched base sheet resistances R SBi was used.
The thickness of the epitaxial Si layers covering vertically the SiGe base were
estimated from the measured junction capacitances of collector-base and
base-emitter, respectively. Thickness and Ge content of the HBT base were
obtained by x-ray diffraction method. Considering the relatively high Ge
content in our base layer in comparison to other authors (e.g. 3,4) ), an
essential point was to evaluate the pipe limited yield by measuring the
collector to emitter leakage current I CE0 of macro devices (emitter area A E = 10 4
µm 2 , external base area A ext = 2 . 10 4 µm 2 ). As non-piped devices we defined
such with a leakage current lower than 10 nA at V CE = 2 V and V BE = 0.
20
15
10
5
XRD Intensity (a.u.)
10
5
-2
10 -2
10
5
-3
10 -3
10
5
-4
10 -4
10
5
-5
10 -5
10 -6
10 -6
-2000 -1000 0
Δ θ (arcsec)
Fig.1:
Ge concentration in the base of an
HBTobtained from XRD rocking curve
(insert) 6) 0 20 40 60 80 100
Depth (nm)
.
Fig.2:
Pipe-limited yield of HBT’s, defined by
a collector-emitter leakage current
criterion.
3. Specification Tolerances and Process Capability Indices
Wafer
0
0 20 40 60 80 100
Both devices and technological processes are specified by a desired target
value (X) and upper and lower specification limits (USL, LSL) of parameters.
The specification tolerance is characterized by the mean values of the
parameters and the value range from -3 s to +3 s (s is their standard
deviation) obtained by suitable measuring methods. The value of 6 s is the
process capability.
The commonly used capability indices 7) are the process potential (C P ) and the
process capability index (C pk ). C P is the ratio of specification tolerance and
60
50
40
30
20
10
Yield of I_CEo
Yield (I_CEo) / %

process capability. C PK considers the difference between target and actual
mean value in relation to the half of specification tolerance. For a stable
technology it is desirable for these parameters to be as high as possible.
For reasonable capability studies, the LSL and USL have to be established
properly. To this purpose we simulated the influence of different parameters
of the Si/SiGe/Si HBT profile on static and dynamic device performance. A
variation of the following epitaxial parameters was considered:
The Germanium content in the base plateau (x), the thickness of SiGe layer
(DGe), the thickness values of low doped emitter and low doped collector
(LDE, LDC), the Boron dose and therefore the R SBi . We calculated the
following device parameters:
The static current gain (B N ), the transit frequency f T and the maximum
oscillation frequency f max , and the noise figure F min .
We obtained the permissible upper and lower variation limits of each epitaxial
parameter not decreasing the f T and f max target values of 10 %, increasing the
F min target of 10 %, and not violating the + 25 % variation window of B N ,
respectively. According to these conditions, we obtained the lower and upper
specification limits of the epitaxy parameters not violating any of the
permissible variation limits of the device parameters considered. The resulting
LSL and USL in relation to the target values are shown in table 1.
4. Results and Conclusions
Fig. 2 shows the yield data reached on processed wafers. It is obviously, that
the device yield is not seriously limited by pipes despite the relative high Ge
content of the HBTs. Defect investigations showed that the layer stacks
overcome epitaxy and post-epitaxial processing including the emitter
annealing ( 800 °C@15 min + 1000°C@ 30 s) without formation of misfit
dislocations. Therefore, threading dislocations were avoided as main source
of pipes in heteroepitaxy.
Fig. 3 demonstrates by means of the distribution of R SBi considering about 10
000 data points, that our RTCVD epitaxy meets both the technological target
and the specification limits. A similar result we obtained for the other
evaluated parameters. For the low doped emitter thickness that is shown in
Fig. 4. The values of C P and C PK obtained for all parameters are shown in
table 1.
Summarizing our results, we demonstrated that essential process capability
indices of LPCVD epitaxy meet the manufacturing requirements for high
frequency devices. Therefore, this kind of epitaxy should be a real alternative
to UHV CVD with respect to process stability and cost for HBT integration into
high volume production (e. g. CMOS).

Tab. 1: Technological targets X, relative upper and lower specification limits
(USL/X, LSL/X), and capability indices C P , C PK of relevant epitaxy
parameters.
Number of Data Points
Parameter X LSL/X USL/X C P C PK
3000
2000
1000
0
LDE
LDC
DGe
x
RSBi
References:
60 nm
120 nm
25 nm
0,20
5000 Ω
Rsbi Distribution
Target
-25 %
-29 %
-50 %
-10 %
-38 %
Mean 4719 Ohm
Sigma 734 Ohm
Cp 1.1
Cpk 0.94
LSL ULS
3000 4000 5000 6000 7000 8000
Rsbi / Ohm
Fig. 3:
Distribution of R SBi including the value of
technological target and specification
limits (LSL, USL). The statistical values
and C P , C PK are inserted.
+42 %
+35 %
+50 %
+10 %
+54 %
1) E. Crabbe et al., IEDM Tech. Dig., pp. 83 - 86, 1993.
2) A. Schüppen et al., IEDM Tech. Dig., pp. 743 - 746, 1995.
3) D. L. Harame et al., IEDM Tech. Dig., pp. 19 - 22, 1992.
4) D. C. Ahlgren et al., IEDM Tech. Dig., pp. 859 - 862, 1996.
5) See, e. g., G. Ritter et al., MRS Symp. Proc., Vol. 387, pp. 341 - 346,
1995.
6) P. Zaumseil, Cryst. Res. Technol. 31(4), pp. 529 - 537, 1996.
7) See, e. g., ed. R. Bowman et al., „Advanced VLSI Fabrication“ (ICE,
1995),
pp. 1017 - 1022.
Number of Data Points
3000
2500
2000
1500
1000
500
1.3
1.6
1.5
1.5
1.1
1.2
1.5
1.4
1.4
0.9
Depletion Layer Width (E-B) Distribution
Target
Mean 48.7 nm
Sigma 4.3 nm
Cp 1.3
Cpk 1.2
LSL ULS
0
30 40 50 60 70
Depletion Layer Width (E-B) / nm
Fig. 4:
Distribution of the thickness values of
low doped emitter obtained by electrical
measurement on the background
of target and specification tolerance
values.