CMOS Production Compatible SiGe Heteroepitaxy for High ... - Imec

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Ge Content (%) 2. Experimental The tested epitaxial layer stacks, consisting of Si-low doped collector, SiGe base, and Si-low doped emitter, were in situ deposited on LOCOS structures in a commercial single-wafer RTCVD reactor. A typical Ge profile is shown in Fig. 1. Transistor parameters primarily influenced by the epitaxial characteristic were measured. To obtain reliable statistics, about 300 similarly processed 4“ wafers were studied. On each wafer, the parameters were measured on 120 chips. As measure for the stability and wafer uniformity of the epitaxial base doping, the pinched base sheet resistances R SBi was used. The thickness of the epitaxial Si layers covering vertically the SiGe base were estimated from the measured junction capacitances of collector-base and base-emitter, respectively. Thickness and Ge content of the HBT base were obtained by x-ray diffraction method. Considering the relatively high Ge content in our base layer in comparison to other authors (e.g. 3,4) ), an essential point was to evaluate the pipe limited yield by measuring the collector to emitter leakage current I CE0 of macro devices (emitter area A E = 10 4 µm 2 , external base area A ext = 2 . 10 4 µm 2 ). As non-piped devices we defined such with a leakage current lower than 10 nA at V CE = 2 V and V BE = 0. 20 15 10 5 XRD Intensity (a.u.) 10 5 -2 10 -2 10 5 -3 10 -3 10 5 -4 10 -4 10 5 -5 10 -5 10 -6 10 -6 -2000 -1000 0 Δ θ (arcsec) Fig.1: Ge concentration in the base of an HBTobtained from XRD rocking curve (insert) 6) 0 20 40 60 80 100 Depth (nm) . Fig.2: Pipe-limited yield of HBT’s, defined by a collector-emitter leakage current criterion. 3. Specification Tolerances and Process Capability Indices Wafer 0 0 20 40 60 80 100 Both devices and technological processes are specified by a desired target value (X) and upper and lower specification limits (USL, LSL) of parameters. The specification tolerance is characterized by the mean values of the parameters and the value range from -3 s to +3 s (s is their standard deviation) obtained by suitable measuring methods. The value of 6 s is the process capability. The commonly used capability indices 7) are the process potential (C P ) and the process capability index (C pk ). C P is the ratio of specification tolerance and 60 50 40 30 20 10 Yield of I_CEo Yield (I_CEo) / %
process capability. C PK considers the difference between target and actual mean value in relation to the half of specification tolerance. For a stable technology it is desirable for these parameters to be as high as possible. For reasonable capability studies, the LSL and USL have to be established properly. To this purpose we simulated the influence of different parameters of the Si/SiGe/Si HBT profile on static and dynamic device performance. A variation of the following epitaxial parameters was considered: The Germanium content in the base plateau (x), the thickness of SiGe layer (DGe), the thickness values of low doped emitter and low doped collector (LDE, LDC), the Boron dose and therefore the R SBi . We calculated the following device parameters: The static current gain (B N ), the transit frequency f T and the maximum oscillation frequency f max , and the noise figure F min . We obtained the permissible upper and lower variation limits of each epitaxial parameter not decreasing the f T and f max target values of 10 %, increasing the F min target of 10 %, and not violating the + 25 % variation window of B N , respectively. According to these conditions, we obtained the lower and upper specification limits of the epitaxy parameters not violating any of the permissible variation limits of the device parameters considered. The resulting LSL and USL in relation to the target values are shown in table 1. 4. Results and Conclusions Fig. 2 shows the yield data reached on processed wafers. It is obviously, that the device yield is not seriously limited by pipes despite the relative high Ge content of the HBTs. Defect investigations showed that the layer stacks overcome epitaxy and post-epitaxial processing including the emitter annealing ( 800 °C@15 min + 1000°C@ 30 s) without formation of misfit dislocations. Therefore, threading dislocations were avoided as main source of pipes in heteroepitaxy. Fig. 3 demonstrates by means of the distribution of R SBi considering about 10 000 data points, that our RTCVD epitaxy meets both the technological target and the specification limits. A similar result we obtained for the other evaluated parameters. For the low doped emitter thickness that is shown in Fig. 4. The values of C P and C PK obtained for all parameters are shown in table 1. Summarizing our results, we demonstrated that essential process capability indices of LPCVD epitaxy meet the manufacturing requirements for high frequency devices. Therefore, this kind of epitaxy should be a real alternative to UHV CVD with respect to process stability and cost for HBT integration into high volume production (e. g. CMOS).
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CMOS Production Compatible SiGe Heteroepitaxy for High ... - Imec

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