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Using FPGAs to Design Gigabit Serial Backplanes - Xilinx

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<strong>Using</strong> <strong>FPGAs</strong> <strong>to</strong><br />

<strong>Design</strong> <strong>Gigabit</strong><br />

<strong>Serial</strong> <strong>Backplanes</strong><br />

April 17, 2002


Outline<br />

•System <strong>Design</strong> Trends<br />

•<strong>Serial</strong> <strong>Backplanes</strong> Architectures<br />

•Building <strong>Serial</strong> <strong>Backplanes</strong> with <strong>FPGAs</strong><br />

A1 - 2


Key System <strong>Design</strong> Trends<br />

•Need for ….<br />

–Easy Scalability of Performance<br />

–Extremely High Availability<br />

–Flexible Architecture<br />

–Use of Standards<br />

• Rapid Time <strong>to</strong> Market<br />

• Reduces Costs<br />

A1 - 3


Merging Communications & Computers<br />

• Communications Systems have serial backplanes<br />

• Computers moving <strong>to</strong> serial backplanes<br />

Database servers<br />

Application servers<br />

1U Web servers<br />

Ethernet Switches<br />

Internet<br />

“Bladed Server”, PICMG 2.16<br />

A1 - 4


<strong>Serial</strong> Standards<br />

• <strong>Serial</strong> Standards<br />

– Fiber Channel 1 Gbps<br />

– Ethernet 1 Gbps<br />

– InfiniBand 2.5 Gbps<br />

• Parallel Standards Going <strong>Serial</strong><br />

– PCI => 3GIO<br />

– RapidIO => <strong>Serial</strong> RapidIO<br />

– ATA => <strong>Serial</strong> ATA<br />

• Channel Bonded <strong>Serial</strong> Standards<br />

– XAUI 10 <strong>Gigabit</strong> Ethernet (4 x 3.125 Gbps)<br />

3GIO<br />

A1 - 5


<strong>Serial</strong> Connectivity = Higher<br />

Bandwidth & Fewer Pins<br />

1 2 3 4 5<br />

50<br />

Example - PCI: 32-bit x 33MHz = 1 Gbps, Shared among 5 clients 250 <strong>to</strong>tal pins<br />

1 2 3 4 5<br />

4<br />

Virtex-II Pro System: 2.5 Gbps x 4 x 5 = 50 Gbps 80 <strong>to</strong>tal pins<br />

Each Client has 2.5 Gbps guaranteed <strong>to</strong> every other Client<br />

50x higher bandwidth with less than 1/3 of the pins<br />

RJG<br />

A1 - 6


Link Rates (bits per sec.)<br />

40G<br />

10G<br />

3.125G<br />

1.25G<br />

622M<br />

155M<br />

•OC-3<br />

1998<br />

<strong>Serial</strong> Link Rates<br />

•OC-12<br />

•FC<br />

•OC-48<br />

•GigE<br />

•OC-192<br />

•FC-2x<br />

•10GE<br />

•FC-10x<br />

•SxI-5<br />

•3GIO<br />

•Infiniband<br />

•Rapid IO<br />

•OC-768<br />

2000 2002 2004<br />

Mainstream Deployment<br />

2006<br />

A1 - 7


<strong>Serial</strong> Topologies<br />

Switched<br />

PICMG 2.16<br />

Full Mesh<br />

PICMG 2.2<br />

PICMG 3.x<br />

A1 - 8


Building <strong>Serial</strong> <strong>Backplanes</strong><br />

Virtex-II<br />

<strong>Gigabit</strong> Ethernet<br />

MAC x2<br />

with <strong>FPGAs</strong><br />

<strong>Gigabit</strong> Ethernet<br />

Phy x2<br />

Switched<br />

PICMG 2.16<br />

A1 - 9


Virtex-II Pro<br />

Platform FPGA<br />

A1 - 10


Virtex-II Pro Rocket I/O<br />

32 / 16 / 8 bits<br />

TXDATA<br />

32 / 16 / 8 bits<br />

RXDATA<br />

Technology<br />

Physical Coding Sublayer Physical Media Attachment<br />

C<br />

R<br />

C<br />

40 – 156.3 MHz<br />

REFCLK<br />

CRC<br />

Elastic<br />

Buffer<br />

(PCS) (PMA)<br />

8B / 10B<br />

Encode<br />

F<br />

I<br />

F<br />

O<br />

Channel Bonding<br />

and<br />

Clock Correction<br />

8B / 10B<br />

Decode<br />

<strong>Serial</strong>izer<br />

TX Clock Genera<strong>to</strong>r<br />

RX Clock Recovery<br />

Deserializer<br />

Comma Det.<br />

Transmitter<br />

Transmit<br />

Buffer<br />

20X Multiplier<br />

Receiver<br />

Receive<br />

Buffer<br />

RX+<br />

RX-<br />

Up <strong>to</strong> sixteen multi-gigabit serial transceivers<br />

Support 622 Mbps <strong>to</strong> 3.125 Gbps full duplex operation<br />

Flexible PCS/PMA feature set<br />

Loop-back<br />

TX+<br />

TX-<br />

A1 - 11


<strong>Xilinx</strong>® Rocket I/O <strong>Serial</strong> Backplane<br />

Interface Technology<br />

•Rocket I/O <strong>Serial</strong> Backplane Interface (RSBI)<br />

Technology<br />

– Simple solution for serial backplane applications<br />

– Consists of two parts<br />

• The RSBI/ “Aurora” link pro<strong>to</strong>col<br />

• An RSBI Reference <strong>Design</strong> (IP core) implementing<br />

that pro<strong>to</strong>col<br />

A1 - 12


RSBI/ “Aurora” Pro<strong>to</strong>col<br />

•An Efficient, Lightweight Pro<strong>to</strong>col <strong>to</strong> Move<br />

Data Point <strong>to</strong> Point across <strong>Serial</strong> Link<br />

•Used <strong>to</strong> transport higher-level pro<strong>to</strong>cols<br />

–Standard pro<strong>to</strong>cols like Ethernet<br />

–Proprietary, cus<strong>to</strong>mer-defined, pro<strong>to</strong>cols<br />

A1 - 13


RSBI Core<br />

• Implements RSBI/ “Aurora” Pro<strong>to</strong>col<br />

• Provides a simple interface for transferring packets<br />

across<br />

– A single gigabit serial link<br />

– Up <strong>to</strong> 16 bonded links<br />

• Minimal Use of Resources (~350 slices)<br />

• Frequency and Technology Independent<br />

• Specifications and Source Code available from<br />

<strong>Xilinx</strong><br />

A1 - 14


RSBI/ “Aurora” Features<br />

• Uses 8B/10B and includes CRC protection<br />

• Transmitter wraps user data in Rocket I/O “Aurora”<br />

pro<strong>to</strong>col<br />

– Handles packet formation<br />

– Sends error notification <strong>to</strong> remote core<br />

• Receiver recovers frames and realigns data<br />

– Strips packet/frame wrappers<br />

– Aligns data on double word boundary<br />

– Moni<strong>to</strong>rs error conditions<br />

A1 - 15


USER<br />

RSBI User Interface<br />

32<br />

SIMPLE<br />

CONTROL<br />

32<br />

RSBI Rocket I/O Block<br />

32<br />

COMPLEX<br />

CONTROL<br />

32<br />

Very<br />

High<br />

Speed<br />

Data<br />

User interface created so no knowledge of Rocket I/O block is necessary<br />

A1 - 16


RSBI Channel Bonding<br />

• All lanes must have passed comma detect before<br />

channel bonding starts<br />

• Uses same technique as 10 <strong>Gigabit</strong> Ethernet and<br />

<strong>Serial</strong> RapidIO<br />

– Sends semi-random IDLE pattern<br />

Channel Bonding Logic<br />

Virtual data<br />

channel<br />

Synchronization of individual channels<br />

in<strong>to</strong> a single large data channel<br />

A1 - 17


• Allows maximum frame size of 8K Unlimited bytes<br />

• 32-bit internal interface<br />

RSBI/ “Aurora”<br />

Implementation Parameters<br />

• Other frame sizes and internal interface widths<br />

planned in future releases<br />

A1 - 18


Error Detection in Hardware<br />

• Errors can be either in Rocket I/O block or link(s)<br />

• Five sources of link failure detected:<br />

– Link physical error threshold overflow<br />

– Channel misalignment<br />

– FIFO overflow<br />

• Receiver or transmitter<br />

– Transmitter sending an illegal K character<br />

• Upon detection of link failure, core resets itself and forces<br />

link partner <strong>to</strong> reset<br />

A1 - 19


RSBI Transmission<br />

• All data frames have a SOP/SOF and EOP/EOF <strong>to</strong><br />

indicate the start and end of packet<br />

• User must send at least 2 DWORDs (8 bytes)<br />

• Core will add pad data <strong>to</strong> allow CRC functionality<br />

• User can not transmit data in increments less than input<br />

width<br />

– Data can now be transmitted in any increment<br />

A1 - 20


RSBI Reception<br />

•Strips off SOP/SOF* and EOP/EOF**<br />

from frame<br />

•Strips off pad data if necessary<br />

•Signals any errors detected<br />

• Checks CRC for correctness<br />

*SOP/F = Starting of Packet/Frame<br />

**EOP/F = End of Packet/Frame<br />

A1 - 21


<strong>Serial</strong> Backplane: Full Mesh<br />

X 15<br />

2VP50<br />

RSBI layer<br />

Rocket I/O Transceivers<br />

<strong>Design</strong> Approach Supporting<br />

16 slot, 3.125 Gbps per link<br />

Full Mesh <strong>Serial</strong> Backplane<br />

A1 - 22


Rocket I/O<br />

Transceiver<br />

Implementing RSBI in<br />

Virtex-II Pro Platform FPGA<br />

FPGA Edi<strong>to</strong>r<br />

View of 2VP7<br />

Implementation in Virtex-II Pro FPGA<br />

• Features<br />

– Up <strong>to</strong> 40 Gbps<br />

– 32-bit user interface<br />

– Low overhead<br />

• Utilization<br />

– 350 Slices<br />

RSBI<br />

Link<br />

Rocket I/O<br />

Interface<br />

Au<strong>to</strong><br />

Negotiation &<br />

Synchronization<br />

Au<strong>to</strong><br />

Negotiation &<br />

Synchronization<br />

RSBI Core<br />

Framer<br />

Framer<br />

Framer<br />

Framer<br />

User<br />

Interface<br />

User<br />

App<br />

A1 - 23


<strong>Serial</strong> Backplane:Private Connection<br />

X 15<br />

2VP50<br />

Parallel<br />

Connection<br />

on line card<br />

X 4<br />

2VP2<br />

4 Transceivers<br />

Channel Bonded<br />

for “Private” board<br />

<strong>to</strong> board connection<br />

A1 - 24


Sample <strong>Serial</strong> Backplane<br />

4<br />

XAUI<br />

Switch<br />

2VP20<br />

Approaches<br />

4<br />

XAUI<br />

Switch<br />

XAUI Core<br />

Rocket I/O Transceivers<br />

Backplane<br />

Switched<br />

A1 - 25


TXD, TXC<br />

RXD, RXC<br />

Implementing XAUI in<br />

Virtex-II Pro FPGA<br />

Transmitter<br />

Receiver<br />

Management Ports<br />

XAUI Core<br />

Deskew<br />

State<br />

Machine<br />

Sync<br />

Sync<br />

Sync<br />

Sync<br />

XAUI_TX_L0<br />

XAUI_RX_L0<br />

XAUI_TX_L1<br />

XAUI_RX_L1<br />

XAUI_TX_L2<br />

XAUI_RX_L2<br />

XAUI_TX_L3<br />

XAUI_RX_L3<br />

XAUI Floorplan –<br />

2VP7<br />

Rocket I/O<br />

Transceivers<br />

• Implementation in V-II Pro<br />

• Uses 4 Rocket I/O Transceivers<br />

– Channel bonding<br />

– 8B/10B encoding<br />

• Utilization<br />

– 800 Slices<br />

A1 - 26


Signal Integrity <strong>Design</strong> Resources<br />

http://www.xilinx.com/signalintegrity<br />

A1 - 27


Power Filtering Network<br />

A1 - 28


Power Filtering Network Components<br />

Capaci<strong>to</strong>rs<br />

C = 0.22uF<br />

Package: 0603 SMT<br />

Dielectric: X7R<br />

Tolerance: 10%<br />

WVDC: 10V<br />

Spacing: Within 1cm of pin<br />

Ferrite Beads<br />

Murata BLM11A102S<br />

Voltage Regula<strong>to</strong>r<br />

Linear Technology LT1963<br />

All parts specified in PCB <strong>Design</strong> Requirements<br />

Voltage Regula<strong>to</strong>r must use circuit specified by manufacturer<br />

A1 - 29


Top of board<br />

VTTX, VTRX<br />

Capaci<strong>to</strong>rs<br />

Ferrite Bead<br />

A1 - 30


AVCCAUXTX, AVCCAUXRX<br />

Bot<strong>to</strong>m of board<br />

FPGA Bypass Caps<br />

Ferrite Bead<br />

Capaci<strong>to</strong>r<br />

A1 - 31


Reference Clock<br />

• Must use EPSON EG-2121CA<br />

– 2.5V LVPECL output oscilla<strong>to</strong>r<br />

– Use according <strong>to</strong> manufacture specifications<br />

• Resis<strong>to</strong>r network for clock input:<br />

R1 510 ohm<br />

R2 130 ohm<br />

R3 25 ohm<br />

R4 100 ohm<br />

A1 - 32


Implementation Resources<br />

• Physical (PCB) <strong>Design</strong> Information<br />

– Signal Integrity Central on <strong>Xilinx</strong> Web Site<br />

(http://www.xilinx.com/signalintegrity)<br />

– Rocket I/O User Guide<br />

– Spice Suite<br />

• RSBI <strong>Design</strong> Information (http://www.xilinx.com/rsbi)<br />

– Specification, Implementation notes<br />

– Source code (Verilog)<br />

– Test bench<br />

• XAUI information (http://www.xilinx.com/connectivity)<br />

– In Networking/Datapath Products (10 <strong>Gigabit</strong> Ethernet)<br />

A1 - 33


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