Using FPGAs to Design Gigabit Serial Backplanes - Xilinx

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Virtex-II Pro Platform FPGA A1 - 10
Virtex-II Pro Rocket I/O 32 / 16 / 8 bits TXDATA 32 / 16 / 8 bits RXDATA Technology Physical Coding Sublayer Physical Media Attachment C R C 40 – 156.3 MHz REFCLK CRC Elastic Buffer (PCS) (PMA) 8B / 10B Encode F I F O Channel Bonding and Clock Correction 8B / 10B Decode Serializer TX Clock Generator RX Clock Recovery Deserializer Comma Det. Transmitter Transmit Buffer 20X Multiplier Receiver Receive Buffer RX+ RX- Up to sixteen multi-gigabit serial transceivers Support 622 Mbps to 3.125 Gbps full duplex operation Flexible PCS/PMA feature set Loop-back TX+ TX- A1 - 11
Page 1 and 2: Using FPGAs to Design Gigabit Seria
Page 3 and 4: Key System Design Trends •Need fo
Page 5 and 6: Serial Standards • Serial Standar
Page 7 and 8: Link Rates (bits per sec.) 40G 10G
Page 9: Building Serial Backplanes Virtex-I
Page 13 and 14: RSBI/ “Aurora” Protocol •An E
Page 15 and 16: RSBI/ “Aurora” Features • Use
Page 17 and 18: RSBI Channel Bonding • All lanes
Page 19 and 20: Error Detection in Hardware • Err
Page 21 and 22: RSBI Reception •Strips off SOP/SO
Page 23 and 24: Rocket I/O Transceiver Implementing
Page 25 and 26: Sample Serial Backplane 4 XAUI Swit
Page 27 and 28: Signal Integrity Design Resources h
Page 29 and 30: Power Filtering Network Components
Page 31 and 32: AVCCAUXTX, AVCCAUXRX Bottom of boar
Page 33 and 34: Implementation Resources • Physic

Using FPGAs to Design Gigabit Serial Backplanes - Xilinx

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