Using FPGAs to Design Gigabit Serial Backplanes - Xilinx
Using FPGAs to Design Gigabit Serial Backplanes - Xilinx
Using FPGAs to Design Gigabit Serial Backplanes - Xilinx
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Rocket I/O<br />
Transceiver<br />
Implementing RSBI in<br />
Virtex-II Pro Platform FPGA<br />
FPGA Edi<strong>to</strong>r<br />
View of 2VP7<br />
Implementation in Virtex-II Pro FPGA<br />
• Features<br />
– Up <strong>to</strong> 40 Gbps<br />
– 32-bit user interface<br />
– Low overhead<br />
• Utilization<br />
– 350 Slices<br />
RSBI<br />
Link<br />
Rocket I/O<br />
Interface<br />
Au<strong>to</strong><br />
Negotiation &<br />
Synchronization<br />
Au<strong>to</strong><br />
Negotiation &<br />
Synchronization<br />
RSBI Core<br />
Framer<br />
Framer<br />
Framer<br />
Framer<br />
User<br />
Interface<br />
User<br />
App<br />
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