Using FPGAs to Design Gigabit Serial Backplanes - Xilinx

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RSBI Transmission • All data frames have a SOP/SOF and EOP/EOF <strong>to</strong> indicate the start and end of packet • User must send at least 2 DWORDs (8 bytes) • Core will add pad data <strong>to</strong> allow CRC functionality • User can not transmit data in increments less than input width – Data can now be transmitted in any increment A1 - 20
RSBI Reception •Strips off SOP/SOF* and EOP/EOF** from frame •Strips off pad data if necessary •Signals any errors detected • Checks CRC for correctness *SOP/F = Starting of Packet/Frame **EOP/F = End of Packet/Frame A1 - 21
Page 1 and 2: Using FPGAs to Design Gigabit Seria
Page 3 and 4: Key System Design Trends •Need fo
Page 5 and 6: Serial Standards • Serial Standar
Page 7 and 8: Link Rates (bits per sec.) 40G 10G
Page 9 and 10: Building Serial Backplanes Virtex-I
Page 11 and 12: Virtex-II Pro Rocket I/O 32 / 16 /
Page 13 and 14: RSBI/ “Aurora” Protocol •An E
Page 15 and 16: RSBI/ “Aurora” Features • Use
Page 17 and 18: RSBI Channel Bonding • All lanes
Page 19: Error Detection in Hardware • Err
Page 23 and 24: Rocket I/O Transceiver Implementing
Page 25 and 26: Sample Serial Backplane 4 XAUI Swit
Page 27 and 28: Signal Integrity Design Resources h
Page 29 and 30: Power Filtering Network Components
Page 31 and 32: AVCCAUXTX, AVCCAUXRX Bottom of boar
Page 33 and 34: Implementation Resources • Physic

Using FPGAs to Design Gigabit Serial Backplanes - Xilinx

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