Using FPGAs to Design Gigabit Serial Backplanes - Xilinx
Using FPGAs to Design Gigabit Serial Backplanes - Xilinx
Using FPGAs to Design Gigabit Serial Backplanes - Xilinx
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RSBI Channel Bonding<br />
• All lanes must have passed comma detect before<br />
channel bonding starts<br />
• Uses same technique as 10 <strong>Gigabit</strong> Ethernet and<br />
<strong>Serial</strong> RapidIO<br />
– Sends semi-random IDLE pattern<br />
Channel Bonding Logic<br />
Virtual data<br />
channel<br />
Synchronization of individual channels<br />
in<strong>to</strong> a single large data channel<br />
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