Using FPGAs to Design Gigabit Serial Backplanes - Xilinx

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Reference Clock • Must use EPSON EG-2121CA – 2.5V LVPECL output oscillator – Use according to manufacture specifications • Resistor network for clock input: R1 510 ohm R2 130 ohm R3 25 ohm R4 100 ohm A1 - 32
Implementation Resources • Physical (PCB) Design Information – Signal Integrity Central on Xilinx Web Site (http://www.xilinx.com/signalintegrity) – Rocket I/O User Guide – Spice Suite • RSBI Design Information (http://www.xilinx.com/rsbi) – Specification, Implementation notes – Source code (Verilog) – Test bench • XAUI information (http://www.xilinx.com/connectivity) – In Networking/Datapath Products (10 Gigabit Ethernet) A1 - 33
Page 1 and 2: Using FPGAs to Design Gigabit Seria
Page 3 and 4: Key System Design Trends •Need fo
Page 5 and 6: Serial Standards • Serial Standar
Page 7 and 8: Link Rates (bits per sec.) 40G 10G
Page 9 and 10: Building Serial Backplanes Virtex-I
Page 11 and 12: Virtex-II Pro Rocket I/O 32 / 16 /
Page 13 and 14: RSBI/ “Aurora” Protocol •An E
Page 15 and 16: RSBI/ “Aurora” Features • Use
Page 17 and 18: RSBI Channel Bonding • All lanes
Page 19 and 20: Error Detection in Hardware • Err
Page 21 and 22: RSBI Reception •Strips off SOP/SO
Page 23 and 24: Rocket I/O Transceiver Implementing
Page 25 and 26: Sample Serial Backplane 4 XAUI Swit
Page 27 and 28: Signal Integrity Design Resources h
Page 29 and 30: Power Filtering Network Components
Page 31: AVCCAUXTX, AVCCAUXRX Bottom of boar

Using FPGAs to Design Gigabit Serial Backplanes - Xilinx

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