Using FPGAs to Design Gigabit Serial Backplanes - Xilinx

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TXD, TXC RXD, RXC Implementing XAUI in Virtex-II Pro FPGA Transmitter Receiver Management Ports XAUI Core Deskew State Machine Sync Sync Sync Sync XAUI_TX_L0 XAUI_RX_L0 XAUI_TX_L1 XAUI_RX_L1 XAUI_TX_L2 XAUI_RX_L2 XAUI_TX_L3 XAUI_RX_L3 XAUI Floorplan – 2VP7 Rocket I/O Transceivers • Implementation in V-II Pro • Uses 4 Rocket I/O Transceivers – Channel bonding – 8B/10B encoding • Utilization – 800 Slices A1 - 26
Signal Integrity <strong>Design</strong> Resources http://www.xilinx.com/signalintegrity A1 - 27
Page 1 and 2: Using FPGAs to Design Gigabit Seria
Page 3 and 4: Key System Design Trends •Need fo
Page 5 and 6: Serial Standards • Serial Standar
Page 7 and 8: Link Rates (bits per sec.) 40G 10G
Page 9 and 10: Building Serial Backplanes Virtex-I
Page 11 and 12: Virtex-II Pro Rocket I/O 32 / 16 /
Page 13 and 14: RSBI/ “Aurora” Protocol •An E
Page 15 and 16: RSBI/ “Aurora” Features • Use
Page 17 and 18: RSBI Channel Bonding • All lanes
Page 19 and 20: Error Detection in Hardware • Err
Page 21 and 22: RSBI Reception •Strips off SOP/SO
Page 23 and 24: Rocket I/O Transceiver Implementing
Page 25: Sample Serial Backplane 4 XAUI Swit
Page 29 and 30: Power Filtering Network Components
Page 31 and 32: AVCCAUXTX, AVCCAUXRX Bottom of boar
Page 33 and 34: Implementation Resources • Physic

Using FPGAs to Design Gigabit Serial Backplanes - Xilinx

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