Using FPGAs to Design Gigabit Serial Backplanes - Xilinx

More documents

Recommendations

Info

• Allows maximum frame size of 8K Unlimited bytes • 32-bit internal interface RSBI/ “Aurora” Implementation Parameters • Other frame sizes and internal interface widths planned in future releases A1 - 18
Error Detection in Hardware • Errors can be either in Rocket I/O block or link(s) • Five sources of link failure detected: – Link physical error threshold overflow – Channel misalignment – FIFO overflow • Receiver or transmitter – Transmitter sending an illegal K character • Upon detection of link failure, core resets itself and forces link partner <strong>to</strong> reset A1 - 19
Page 1 and 2: Using FPGAs to Design Gigabit Seria
Page 3 and 4: Key System Design Trends •Need fo
Page 5 and 6: Serial Standards • Serial Standar
Page 7 and 8: Link Rates (bits per sec.) 40G 10G
Page 9 and 10: Building Serial Backplanes Virtex-I
Page 11 and 12: Virtex-II Pro Rocket I/O 32 / 16 /
Page 13 and 14: RSBI/ “Aurora” Protocol •An E
Page 15 and 16: RSBI/ “Aurora” Features • Use
Page 17: RSBI Channel Bonding • All lanes
Page 21 and 22: RSBI Reception •Strips off SOP/SO
Page 23 and 24: Rocket I/O Transceiver Implementing
Page 25 and 26: Sample Serial Backplane 4 XAUI Swit
Page 27 and 28: Signal Integrity Design Resources h
Page 29 and 30: Power Filtering Network Components
Page 31 and 32: AVCCAUXTX, AVCCAUXRX Bottom of boar
Page 33 and 34: Implementation Resources • Physic

Using FPGAs to Design Gigabit Serial Backplanes - Xilinx

Create successful ePaper yourself

Delete template?

Save as template?