Using FPGAs to Design Gigabit Serial Backplanes - Xilinx
Using FPGAs to Design Gigabit Serial Backplanes - Xilinx
Using FPGAs to Design Gigabit Serial Backplanes - Xilinx
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<strong>Xilinx</strong>® Rocket I/O <strong>Serial</strong> Backplane<br />
Interface Technology<br />
•Rocket I/O <strong>Serial</strong> Backplane Interface (RSBI)<br />
Technology<br />
– Simple solution for serial backplane applications<br />
– Consists of two parts<br />
• The RSBI/ “Aurora” link pro<strong>to</strong>col<br />
• An RSBI Reference <strong>Design</strong> (IP core) implementing<br />
that pro<strong>to</strong>col<br />
A1 - 12
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