Using FPGAs to Design Gigabit Serial Backplanes - Xilinx

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Power Filtering Network A1 - 28
Power Filtering Network Components Capacitors C = 0.22uF Package: 0603 SMT Dielectric: X7R Tolerance: 10% WVDC: 10V Spacing: Within 1cm of pin Ferrite Beads Murata BLM11A102S Voltage Regulator Linear Technology LT1963 All parts specified in PCB Design Requirements Voltage Regulator must use circuit specified by manufacturer A1 - 29
Page 1 and 2: Using FPGAs to Design Gigabit Seria
Page 3 and 4: Key System Design Trends •Need fo
Page 5 and 6: Serial Standards • Serial Standar
Page 7 and 8: Link Rates (bits per sec.) 40G 10G
Page 9 and 10: Building Serial Backplanes Virtex-I
Page 11 and 12: Virtex-II Pro Rocket I/O 32 / 16 /
Page 13 and 14: RSBI/ “Aurora” Protocol •An E
Page 15 and 16: RSBI/ “Aurora” Features • Use
Page 17 and 18: RSBI Channel Bonding • All lanes
Page 19 and 20: Error Detection in Hardware • Err
Page 21 and 22: RSBI Reception •Strips off SOP/SO
Page 23 and 24: Rocket I/O Transceiver Implementing
Page 25 and 26: Sample Serial Backplane 4 XAUI Swit
Page 27: Signal Integrity Design Resources h
Page 31 and 32: AVCCAUXTX, AVCCAUXRX Bottom of boar
Page 33 and 34: Implementation Resources • Physic

Using FPGAs to Design Gigabit Serial Backplanes - Xilinx

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