- Page 1 and 2: LogiCORE IP 10-Gigabit Ethernet MAC
- Page 3 and 4: Table of Contents Revision History
- Page 5 and 6: Interfacing to the Receive AXI4-Str
- Page 7 and 8: Chapter 13: Detailed Example Design
- Page 9 and 10: Schedule of Figures Preface: About
- Page 11 and 12: Chapter 13: Detailed Example Design
- Page 13 and 14: Schedule of Tables Preface: About T
- Page 15 and 16: Appendix A: Verification and Intero
- Page 17 and 18: About This Guide Guide Contents Pre
- Page 19 and 20: Italic font Dark Shading Square bra
- Page 21: Acronym Description MDC Management
- Page 25 and 26: Licensing the Core Before you Begin
- Page 27 and 28: Core Architecture System Overview X
- Page 29 and 30: Functional Description Functional D
- Page 31 and 32: Core Interfaces and Modules AXI4-St
- Page 33 and 34: Management Interface Core Interface
- Page 35 and 36: Clocking and Reset Signals and Modu
- Page 37 and 38: Customizing and Generating Core GUI
- Page 39 and 40: Parameter Values in the XCO File Ou
- Page 41 and 42: Designing with the Core General Des
- Page 43 and 44: Chapter 6 Interfacing to the Core:
- Page 45 and 46: In-Band Ethernet Frame Fields Inter
- Page 47 and 48: X-Ref Target - Figure 6-3 X-Ref Tar
- Page 49 and 50: X-Ref Target - Figure 6-6 tx_clk0 t
- Page 51 and 52: X-Ref Target - Figure 6-9 VLAN Tagg
- Page 53 and 54: X-Ref Target - Figure 6-11 tx_clk0
- Page 55 and 56: X-Ref Target - Figure 6-12 rx_clk r
- Page 57 and 58: X-Ref Target - Figure 6-14 rx_clk r
- Page 59 and 60: X-Ref Target - Figure 6-16 rx_clk r
- Page 61 and 62: Sending and Receiving Flow Control
- Page 63 and 64: Chapter 7 Interfacing to the Core:
- Page 65 and 66: X-Ref Target - Figure 7-2 s_axi_acl
- Page 67 and 68: Table 7-2: Statistics Counters (Con
- Page 69 and 70: Table 7-3: Configuration Registers
- Page 71 and 72: Table 7-6: Transmitter Configuratio
- Page 73 and 74:
Table 7-9: Receiver MTU Configurati
- Page 75 and 76:
Table 7-15: MDIO Configuration Word
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mdc mdio mdc mdio mdc mdio Z Z Set
- Page 79 and 80:
The Configuration and Status Vector
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Table 7-21: rx_configuration_vector
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Receive Table 7-23: Transmit Statis
- Page 85 and 86:
Table 7-24: Receive Statistics Vect
- Page 87 and 88:
Using Flow Control Overview of Flow
- Page 89 and 90:
Flow Control Operation of the 10-Gi
- Page 91 and 92:
Flow Control Implementation Example
- Page 93 and 94:
Constraining the Core Chapter 9 Thi
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Management Constraints ############
- Page 97 and 98:
MDIO Interface I/O Constraints MDIO
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Special Design Considerations Reset
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Pin Location Considerations for XGM
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X-Ref Target - Figure 10-4 refclk_p
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X-Ref Target - Figure 10-6 refclk_p
- Page 107 and 108:
Interfacing to the 10-Gigabit Ether
- Page 109 and 110:
Behavior of the Evaluation Core in
- Page 111 and 112:
Implementing Your Design Synthesis
- Page 113 and 114:
Static Timing Analysis Post-Impleme
- Page 115 and 116:
Quick Start Example Design Introduc
- Page 117 and 118:
Implementation Simulation Implement
- Page 119 and 120:
Detailed Example Design Chapter 13
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Directory and File Contents The di
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example_design/fifo Directory and F
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simulation/functional Directory and
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Implementation and Test Scripts Imp
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10-Gigabit Ethernet MAC with Extern
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10-Gigabit Ethernet MAC with 64-bit
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AXI4-Lite to IPIF Converter Block X
- Page 135 and 136:
Verification and Interoperability A
- Page 137 and 138:
Appendix B Calculating the DCM Fixe
- Page 139 and 140:
Core Latency Transmit Path Latency