Xilinx UG773 LogiCORE IP 10-Gigabit Ethernet MAC v11.1, User ...

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Chapter 6: Interfacing to the Core: Data Interfaces The MAC core will substitute the IEEE standard preamble with that supplied by the client logic. Figure 6-8 shows the transmission of a frame with custom preamble (P1 to P7) at the XGMII interface. X-Ref Target - Figure 6-8. txclk Lane 3 (txd[31:24]) Lane 2 (txd[23:16]) Lane 1 (txd[15:8]) Lane 0 (txd[7:0]) txc[3:0] Figure 6-8: XGMII Frame Transmission of Custom Preamble 50 www.xilinx.com 10-Gigabit Ethernet MAC User Guide UG773 March 1, 2011 0x07 0x07 0x07 IDLE P3 P2 P1 0x07 0xFB PREAMBLE #1 P7 P6 P5 P4 PREAMBLE #2 DA DA DA DA 0xF 0x1 0x0 0x0 DATA
X-Ref Target - Figure 6-9 VLAN Tagged Frames tx_clk0 tx_axis_tvalid tx_axis_tready tx_axis_tdata[7:0] tx_axis_tdata[15:8] tx_axis_tdata[23:16] tx_axis_tdata[31:24] tx_axis_tdata[39:32] tx_axis_tdata[47:40] tx_axis_tdata[55:48] tx_axis_tdata[63:56] tx_axis_tkeep[7:0] tx_axis_tlast Interfacing to the Transmit AXI4-Stream Interface Transmission of a VLAN tagged frame (if enabled) is shown in Figure 6-9. The handshaking signals across the interface do not change; however, the VLAN type tag 81-00 must be supplied by the client to signify that the frame is VLAN tagged. The client also supplies the two bytes of Tag Control Information, V1 and V2, at the appropriate times in the data stream. Additional information about the contents of these two bytes is available in IEEE 802.3-2008. DA SA L/T D D D DA SA L/T D D D DA SA L/T D D D DA SA L/T D D D DA SA D D D D DA SA D D D D DA SA D D D D DA SA D D D D DA 81 D D D DA 81 D D D D DA 00 D D D DA 00 D D D SA V1 D D D SA V1 D D D SA V2 D D D SA V2 D D D 0x00 0xFF 0x0F 0x00 0xFF 0x1F Figure 6-9: VLAN Tagged Frame Transmission Transmitter Maximum Permitted Frame Length The maximum legal length of a frame specified in IEEE 802.3-2008 is 1518 bytes for non- VLAN tagged frames. VLAN tagged frames might be extended to 1522 bytes. When jumbo frame handling is disabled and the client attempts to transmit a frame which exceeds the maximum legal length, the MAC core will insert an error code to corrupt the current frame and the frame will be truncated to the maximum legal length. When jumbo frame handling is enabled, frames which are longer than the legal maximum are transmitted error free. If required, a custom Maximum Transmission Unit (MTU) can be programmed into the core. This allows the transmission of frames up to the programmed MTU size by the core, rather than the 1518/1522 byte limit. The programmed MTU must be equal to or greater than 1518 bytes. Any Frame transmitted greater than the MTU Frame Size, if Jumbo Frame is disabled, is signaled as a bad frame; error codes are inserted and the frame is truncated. For details on enabling and disabling jumbo frame handling, see Configuration Registers in Chapter 7. Note: If Jumbo Enable and MTU Frame Transfer Enable are enabled at the same time, the Jumbo Enable takes precedence. 10-Gigabit Ethernet MAC User Guide www.xilinx.com 51 UG773 March 1, 2011
Page 1 and 2: LogiCORE IP 10-Gigabit Ethernet MAC
Page 3 and 4: Table of Contents Revision History
Page 5 and 6: Interfacing to the Receive AXI4-Str
Page 7 and 8: Chapter 13: Detailed Example Design
Page 9 and 10: Schedule of Figures Preface: About
Page 11 and 12: Chapter 13: Detailed Example Design
Page 13 and 14: Schedule of Tables Preface: About T
Page 15 and 16: Appendix A: Verification and Intero
Page 17 and 18: About This Guide Guide Contents Pre
Page 19 and 20: Italic font Dark Shading Square bra
Page 21 and 22: Acronym Description MDC Management
Page 23 and 24: Introduction System Requirements Ab
Page 25 and 26: Licensing the Core Before you Begin
Page 27 and 28: Core Architecture System Overview X
Page 29 and 30: Functional Description Functional D
Page 31 and 32: Core Interfaces and Modules AXI4-St
Page 33 and 34: Management Interface Core Interface
Page 35 and 36: Clocking and Reset Signals and Modu
Page 37 and 38: Customizing and Generating Core GUI
Page 39 and 40: Parameter Values in the XCO File Ou
Page 41 and 42: Designing with the Core General Des
Page 43 and 44: Chapter 6 Interfacing to the Core:
Page 45 and 46: In-Band Ethernet Frame Fields Inter
Page 47 and 48: X-Ref Target - Figure 6-3 X-Ref Tar
Page 49: X-Ref Target - Figure 6-6 tx_clk0 t
Page 53 and 54: X-Ref Target - Figure 6-11 tx_clk0
Page 55 and 56: X-Ref Target - Figure 6-12 rx_clk r
Page 61 and 62: Sending and Receiving Flow Control
Page 63 and 64: Chapter 7 Interfacing to the Core:
Page 65 and 66: X-Ref Target - Figure 7-2 s_axi_acl
Page 67 and 68: Table 7-2: Statistics Counters (Con
Page 69 and 70: Table 7-3: Configuration Registers
Page 71 and 72: Table 7-6: Transmitter Configuratio
Page 73 and 74: Table 7-9: Receiver MTU Configurati
Page 75 and 76: Table 7-15: MDIO Configuration Word
Page 77 and 78: mdc mdio mdc mdio mdc mdio Z Z Set
Page 79 and 80: The Configuration and Status Vector
Page 81 and 82: Table 7-21: rx_configuration_vector
Page 83 and 84: Receive Table 7-23: Transmit Statis
Page 85 and 86: Table 7-24: Receive Statistics Vect
Page 87 and 88: Using Flow Control Overview of Flow
Page 89 and 90: Flow Control Operation of the 10-Gi
Page 91 and 92: Flow Control Implementation Example
Page 93 and 94: Constraining the Core Chapter 9 Thi
Page 95 and 96: Management Constraints ############
Page 97 and 98: MDIO Interface I/O Constraints MDIO
Page 99 and 100: Special Design Considerations Reset
Page 101 and 102:
Pin Location Considerations for XGM
Page 103 and 104:
X-Ref Target - Figure 10-4 refclk_p
Page 105 and 106:
X-Ref Target - Figure 10-6 refclk_p
Page 107 and 108:
Interfacing to the 10-Gigabit Ether
Page 109 and 110:
Behavior of the Evaluation Core in
Page 111 and 112:
Implementing Your Design Synthesis
Page 113 and 114:
Static Timing Analysis Post-Impleme
Page 115 and 116:
Quick Start Example Design Introduc
Page 117 and 118:
Implementation Simulation Implement
Page 119 and 120:
Detailed Example Design Chapter 13
Page 121 and 122:
Directory and File Contents The di
Page 123 and 124:
example_design/fifo Directory and F
Page 125 and 126:
simulation/functional Directory and
Page 127 and 128:
Implementation and Test Scripts Imp
Page 129 and 130:
10-Gigabit Ethernet MAC with Extern
Page 131 and 132:
10-Gigabit Ethernet MAC with 64-bit
Page 133 and 134:
AXI4-Lite to IPIF Converter Block X
Page 135 and 136:
Verification and Interoperability A
Page 137 and 138:
Appendix B Calculating the DCM Fixe
Page 139 and 140:
Core Latency Transmit Path Latency
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