Xilinx UG773 LogiCORE IP 10-Gigabit Ethernet MAC v11.1, User ...

Chapter 3: Core Architecture
X-Ref Target - Figure 3-3
User
Logic
(FIFO
Example
Design)
The 10-Gigabit Ethernet MAC core is designed to be easily attached to the Xilinx® XAUI
core available at the XAUI product page; this gives the advantage over XGMII of reduced
pin count and improved operating distance. Figure 3-3 shows the two cores in a system
using an XPAK optical module. In this case, the XGMII interface is omitted from the 10-
Gigabit Ethernet MAC core at customization time and the internal FPGA logic interface is
used to interface to the XAUI core.
10-Gigabit
Ethernet
MAC Core
XAUI
Core
XPAK Optical Module
low speed management signals
Figure 3-3: 10-Gigabit Ethernet MAC Core Used with Xilinx XAUI Core
See Interfacing to the Xilinx XAUI Core in Chapter 10 for details on using the two cores
together in a system.
The 10-Gigabit Ethernet MAC core can also be easily attached to the Xilinx RXAUI core
and the Xilinx 10G Ethernet PCS/PMA core. See Interfacing with the RXAUI Core and
Interfacing to the 10-Gigabit Ethernet PCS/PMA Core in Chapter 10 for details.
28 www.xilinx.com 10-Gigabit Ethernet MAC User Guide
UG773 March 1, 2011