Xilinx UG773 LogiCORE IP 10-Gigabit Ethernet MAC v11.1, User ...
Xilinx UG773 LogiCORE IP 10-Gigabit Ethernet MAC v11.1, User ...
Xilinx UG773 LogiCORE IP 10-Gigabit Ethernet MAC v11.1, User ...
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Chapter 3: Core Architecture<br />
Configuration and Status Signals<br />
MDIO Interface<br />
Statistic Vectors<br />
If the Management Interface is omitted at core customization time, configuration and<br />
status vectors are exposed by the core. This allows you to configure the core by statically or<br />
dynamically driving the constituent bits of the port. Table 3-6 describes the configuration<br />
and Status signals. See Chapter 7, Interfacing to the Core: Management Interface for details<br />
on this signal, including a breakdown of the configuration and status vector bits.<br />
Table 3-6: Configuration and Status Signals<br />
Name Direction Description<br />
tx_configuration_vector[79:0] Input Configuration signals for the Transmitter<br />
rx_configuration_vector[79:0] Input Configuration signals for the Receiver<br />
status_vector[1:0] Output Status signals for the core<br />
The MDIO Interface signals are shown in Table 3-7. See Chapter 7, Interfacing to the Core:<br />
Management Interface for details on the use of this interface.<br />
Table 3-7: MDIO Interface Port Descriptions<br />
Name Direction Description<br />
mdc Output MDIO clock<br />
mdio_in Input MDIO input<br />
mdio_out Output MDIO output<br />
mdio_tri Output MDIO 3-state. ‘1’ disconnects the output driver from the<br />
MDIO bus.<br />
In addition to the statistic counters described in Management Interface in Chapter 3, there<br />
are two statistics vector outputs on the core netlist that are used to signal the core state.<br />
These vectors are actually used as the inputs of the counter logic internal to the core; so if<br />
you omit the statistic counters at the CORE Generator software customization stage, a<br />
relevant subset can be implemented in user logic. The signals are shown in Table 3-8. The<br />
contents of the vectors themselves are described in Chapter 7, Interfacing to the Core:<br />
Management Interface.<br />
Table 3-8: Statistic Vector Signals<br />
Name Direction Description<br />
tx_statistics_vector[24:0] Output Aggregated statistics flags for<br />
transmitted frame.<br />
tx_statistics_valid Output Valid strobe for tx_statistics_vector.<br />
rx_statistics_vector[28:0] Output Aggregated statistics flags for<br />
received frames.<br />
rx_statistics_valid Output Valid strobe for rx_statistics_vector.<br />
34 www.xilinx.com <strong>10</strong>-<strong>Gigabit</strong> <strong>Ethernet</strong> <strong>MAC</strong> <strong>User</strong> Guide<br />
<strong>UG773</strong> March 1, 2011