Xilinx UG773 LogiCORE IP 10-Gigabit Ethernet MAC v11.1, User ...

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Chapter 6: Interfacing to the Core: Data Interfaces X-Ref Target - Figure 6-5 tx_clk0 tx_axis_tvalid tx_axis_tready tx_axis_tdata[7:0] tx_axis_tdata[15:8] tx_axis_tdata[23:16] tx_axis_tdata[31:24] tx_axis_tdata[39:32] tx_axis_tdata[47:40] tx_axis_tdata[55:48] tx_axis_tdata[63:56] tx_axis_tkeep[7:0] tx_axis_tlast Back-to-Back Continuous Transfers Continuous data transfer on Transmit AXI4-Stream interface is possible, as the signal tx_axis_tvalid can remain continuously HIGH, with packet boundaries defined solely by tx_axis_tlast asserted for the end of the Ethernet packet. However, the MAC core can defer the tx_axis_tready acknowledgement signal to comply with the inter-packet gap requirements on the XGMII side of the core. DA SA D D D D DA SA D D D D D DA SA D D D D DA SA D D D D D DA SA D D D D DA SA D D D D D DA SA D D D D DA SA D D D D D DA L/T D D D DA L/T D D D D D DA L/T D D D DA L/T D D D D SA D D D D SA D D D D D SA D D D D SA D D D D D 0x00 0xFF 0x0F 0xFF 0xFF 0x1F Figure 6-5: Back-to-Back Continuous Transfer on Transmit Client Interface 48 www.xilinx.com 10-Gigabit Ethernet MAC User Guide UG773 March 1, 2011
X-Ref Target - Figure 6-6 tx_clk0 tx_axis_tvalid tx_axis_tready tx_axis_tdata[7:0] tx_axis_tdata[15:8] tx_axis_tdata[23:16] tx_axis_tdata[31:24] tx_axis_tdata[39:32] tx_axis_tdata[47:40] tx_axis_tdata[55:48] tx_axis_tdata[63:56] tx_axis_tkeep[7:0] tx_axis_tlast custom_preamble_en X-Ref Target - Figure 6-7 Transmission of Custom Preamble tx_clk0 tx_axis_tvalid tx_axis_tready tx_axis_tdata[7:0] tx_axis_tdata[15:8] tx_axis_tdata[23:16] tx_axis_tdata[31:24] tx_axis_tdata[39:32] tx_axis_tdata[47:40] tx_axis_tdata[55:48] tx_axis_tdata[63:56] tx_axis_tkeep[7:0] tx_axis_tlast custom_preamble_en Interfacing to the Transmit AXI4-Stream Interface You can elect to use a custom preamble field. If this function is selected (via a configuration bit, see Configuration Registers in Chapter 7), the standard preamble field can be substituted for custom data. The custom data must be supplied on tx_axis_tdata[63:8] in the first column when tx_axis_tvalid is first asserted HIGH. Transmission of Custom Preamble can happen in both continuous and non-continuous mode of tx_axis_tvalid. Figure 6-6 shows a frame presented at the Transmit Client Interface with a custom preamble where P1 to P7 denote the custom data bytes when tx_axis_tvalid is deasserted after tx_axis_tlast. Figure 6-7 illustrates the transmission of a custom preamble when tx_axis_tvalid remains asserted after tx_axis_tlast is asserted. S DA SA D D D S DA SA D D D D P DA SA D D D P DA SA D D D D P DA SA D D D P DA SA D D D D P DA SA D D D P DA SA D D D D P DA L/T D D P DA L/T D D D D P DA L/T D D P DA L/T D D D P SA D D D P SA D D D D P SA D D D P SA D D D D 0x00 0xFF 0xFF 0x0F 0x00 0xFF 0XFF 0x1F Figure 6-6: Transmission of Custom Preamble in the Non-Continuous Case S DA SA D D D S DA SA D D D D P DA SA D D D P DA SA D D D D P DA SA D D D P DA SA D D D D P DA SA D D D P DA SA D D D D P DA L/T D D P DA L/T D D D D P DA L/T D D P DA L/T D D D P SA D D D P SA D D D D P SA D D D P SA D D D D 0x00 0xFF 0xFF 0xFF 0x0F 0xFF 0xFF 0x1F Figure 6-7: Transmission of Custom Preamble in the Continuous Case 10-Gigabit Ethernet MAC User Guide www.xilinx.com 49 UG773 March 1, 2011
Page 1 and 2: LogiCORE IP 10-Gigabit Ethernet MAC
Page 3 and 4: Table of Contents Revision History
Page 5 and 6: Interfacing to the Receive AXI4-Str
Page 7 and 8: Chapter 13: Detailed Example Design
Page 9 and 10: Schedule of Figures Preface: About
Page 11 and 12: Chapter 13: Detailed Example Design
Page 13 and 14: Schedule of Tables Preface: About T
Page 15 and 16: Appendix A: Verification and Intero
Page 17 and 18: About This Guide Guide Contents Pre
Page 19 and 20: Italic font Dark Shading Square bra
Page 21 and 22: Acronym Description MDC Management
Page 23 and 24: Introduction System Requirements Ab
Page 25 and 26: Licensing the Core Before you Begin
Page 27 and 28: Core Architecture System Overview X
Page 29 and 30: Functional Description Functional D
Page 31 and 32: Core Interfaces and Modules AXI4-St
Page 33 and 34: Management Interface Core Interface
Page 35 and 36: Clocking and Reset Signals and Modu
Page 37 and 38: Customizing and Generating Core GUI
Page 39 and 40: Parameter Values in the XCO File Ou
Page 41 and 42: Designing with the Core General Des
Page 43 and 44: Chapter 6 Interfacing to the Core:
Page 45 and 46: In-Band Ethernet Frame Fields Inter
Page 47: X-Ref Target - Figure 6-3 X-Ref Tar
Page 51 and 52: X-Ref Target - Figure 6-9 VLAN Tagg
Page 53 and 54: X-Ref Target - Figure 6-11 tx_clk0
Page 55 and 56: X-Ref Target - Figure 6-12 rx_clk r
Page 61 and 62: Sending and Receiving Flow Control
Page 63 and 64: Chapter 7 Interfacing to the Core:
Page 65 and 66: X-Ref Target - Figure 7-2 s_axi_acl
Page 67 and 68: Table 7-2: Statistics Counters (Con
Page 69 and 70: Table 7-3: Configuration Registers
Page 71 and 72: Table 7-6: Transmitter Configuratio
Page 73 and 74: Table 7-9: Receiver MTU Configurati
Page 75 and 76: Table 7-15: MDIO Configuration Word
Page 77 and 78: mdc mdio mdc mdio mdc mdio Z Z Set
Page 79 and 80: The Configuration and Status Vector
Page 81 and 82: Table 7-21: rx_configuration_vector
Page 83 and 84: Receive Table 7-23: Transmit Statis
Page 85 and 86: Table 7-24: Receive Statistics Vect
Page 87 and 88: Using Flow Control Overview of Flow
Page 89 and 90: Flow Control Operation of the 10-Gi
Page 91 and 92: Flow Control Implementation Example
Page 93 and 94: Constraining the Core Chapter 9 Thi
Page 95 and 96: Management Constraints ############
Page 97 and 98: MDIO Interface I/O Constraints MDIO
Page 99 and 100:
Special Design Considerations Reset
Page 101 and 102:
Pin Location Considerations for XGM
Page 103 and 104:
X-Ref Target - Figure 10-4 refclk_p
Page 105 and 106:
X-Ref Target - Figure 10-6 refclk_p
Page 107 and 108:
Interfacing to the 10-Gigabit Ether
Page 109 and 110:
Behavior of the Evaluation Core in
Page 111 and 112:
Implementing Your Design Synthesis
Page 113 and 114:
Static Timing Analysis Post-Impleme
Page 115 and 116:
Quick Start Example Design Introduc
Page 117 and 118:
Implementation Simulation Implement
Page 119 and 120:
Detailed Example Design Chapter 13
Page 121 and 122:
Directory and File Contents The di
Page 123 and 124:
example_design/fifo Directory and F
Page 125 and 126:
simulation/functional Directory and
Page 127 and 128:
Implementation and Test Scripts Imp
Page 129 and 130:
10-Gigabit Ethernet MAC with Extern
Page 131 and 132:
10-Gigabit Ethernet MAC with 64-bit
Page 133 and 134:
AXI4-Lite to IPIF Converter Block X
Page 135 and 136:
Verification and Interoperability A
Page 137 and 138:
Appendix B Calculating the DCM Fixe
Page 139 and 140:
Core Latency Transmit Path Latency
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