Xilinx UG773 LogiCORE IP 10-Gigabit Ethernet MAC v11.1, User ...

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Chapter 3: Core Architecture Flow Control Interface The flow control interface is used to initiate the transmission of flow control frames from the core. The ports associated with this interface are shown in Table 3-3. Table 3-3: Flow Control Interface Ports Name Direction Description pause_req Input Request that a flow control frame is emitted from the MAC core. pause_val[15:0] Input Pause value field for flow control frame to be sent when pause_req asserted. 32-bit XGMII PHY Interface or 64-bit SDR PHY Interface This interface is used to connect to the physical layer, whether this is a separate device or implemented in the FPGA beside the MAC core. Table 3-4 shows the ports associated with this interface. The PHY interface can be a 32-bit DDR XGMII interface a or 64-bit SDR interface, depending on the customization of the core. However, the netlist ports are always the same width and the translation between 32-bit and 64-bit is performed in the HDL wrapper, if required. Table 3-4: PHY Interface Port Descriptions Name Direction Description xgmii_txd[63:0] Output Transmit data to PHY xgmii_txc[7:0] Output Transmit control to PHY xgmii_rxd[63:0] Input Received data from PHY xgmii_rxc[7:0] Input Received control from PHY 32 www.xilinx.com 10-Gigabit Ethernet MAC User Guide UG773 March 1, 2011
Management Interface Core Interfaces and Modules Configuration of the core, access to the statistics block, access to the MDIO port, and access to the interrupt block can be provided through the Management Interface, a 32-bit AXI4- Lite interface independent of the Ethernet datapath. Table 3-5 defines the ports associated with the Management Interface. Table 3-5: Management Interface Port Descriptions Name Direction Description s_axi_aclk IN AXI4-Lite clock. Range between 10 MHz and 156.25 MHz s_axi_aresetn IN Asynchronous active low reset s_axi_awaddr[31:0] IN Write address Bus s_axi_awvalid IN Write address valid s_axi_awready OUT Write address acknowledge s_axi_wdata[31:0] IN Write data bus s_axi_wvalid OUT Write data valid s_axi_wready OUT Write data acknowledge s_axi_bresp[1:0] OUT Write transaction response s_axi_bvalid OUT Write response valid s_axi_bready IN Write response acknowledge s_axi_araddr[31:0] IN Read address Bus s_axi_arvalid IN Read address valid s_axi_arready OUT Read address acknowledge s_axi_rdata[31:0] OUT Read data output s_axi_rresp[1:0] OUT Read data response s_axi_rvalid OUT Read data/response valid s_axi_rready IN Read data acknowledge The Management Interface can be omitted at core customization stage; if omitted, configuration_vector_tx/rx is available instead. 10-Gigabit Ethernet MAC User Guide www.xilinx.com 33 UG773 March 1, 2011
Page 1 and 2: LogiCORE IP 10-Gigabit Ethernet MAC
Page 3 and 4: Table of Contents Revision History
Page 5 and 6: Interfacing to the Receive AXI4-Str
Page 7 and 8: Chapter 13: Detailed Example Design
Page 9 and 10: Schedule of Figures Preface: About
Page 11 and 12: Chapter 13: Detailed Example Design
Page 13 and 14: Schedule of Tables Preface: About T
Page 15 and 16: Appendix A: Verification and Intero
Page 17 and 18: About This Guide Guide Contents Pre
Page 19 and 20: Italic font Dark Shading Square bra
Page 21 and 22: Acronym Description MDC Management
Page 23 and 24: Introduction System Requirements Ab
Page 25 and 26: Licensing the Core Before you Begin
Page 27 and 28: Core Architecture System Overview X
Page 29 and 30: Functional Description Functional D
Page 31: Core Interfaces and Modules AXI4-St
Page 35 and 36: Clocking and Reset Signals and Modu
Page 37 and 38: Customizing and Generating Core GUI
Page 39 and 40: Parameter Values in the XCO File Ou
Page 41 and 42: Designing with the Core General Des
Page 43 and 44: Chapter 6 Interfacing to the Core:
Page 45 and 46: In-Band Ethernet Frame Fields Inter
Page 47 and 48: X-Ref Target - Figure 6-3 X-Ref Tar
Page 49 and 50: X-Ref Target - Figure 6-6 tx_clk0 t
Page 51 and 52: X-Ref Target - Figure 6-9 VLAN Tagg
Page 53 and 54: X-Ref Target - Figure 6-11 tx_clk0
Page 55 and 56: X-Ref Target - Figure 6-12 rx_clk r
Page 61 and 62: Sending and Receiving Flow Control
Page 63 and 64: Chapter 7 Interfacing to the Core:
Page 65 and 66: X-Ref Target - Figure 7-2 s_axi_acl
Page 67 and 68: Table 7-2: Statistics Counters (Con
Page 69 and 70: Table 7-3: Configuration Registers
Page 71 and 72: Table 7-6: Transmitter Configuratio
Page 73 and 74: Table 7-9: Receiver MTU Configurati
Page 75 and 76: Table 7-15: MDIO Configuration Word
Page 77 and 78: mdc mdio mdc mdio mdc mdio Z Z Set
Page 79 and 80: The Configuration and Status Vector
Page 81 and 82: Table 7-21: rx_configuration_vector
Page 83 and 84:
Receive Table 7-23: Transmit Statis
Page 85 and 86:
Table 7-24: Receive Statistics Vect
Page 87 and 88:
Using Flow Control Overview of Flow
Page 89 and 90:
Flow Control Operation of the 10-Gi
Page 91 and 92:
Flow Control Implementation Example
Page 93 and 94:
Constraining the Core Chapter 9 Thi
Page 95 and 96:
Management Constraints ############
Page 97 and 98:
MDIO Interface I/O Constraints MDIO
Page 99 and 100:
Special Design Considerations Reset
Page 101 and 102:
Pin Location Considerations for XGM
Page 103 and 104:
X-Ref Target - Figure 10-4 refclk_p
Page 105 and 106:
X-Ref Target - Figure 10-6 refclk_p
Page 107 and 108:
Interfacing to the 10-Gigabit Ether
Page 109 and 110:
Behavior of the Evaluation Core in
Page 111 and 112:
Implementing Your Design Synthesis
Page 113 and 114:
Static Timing Analysis Post-Impleme
Page 115 and 116:
Quick Start Example Design Introduc
Page 117 and 118:
Implementation Simulation Implement
Page 119 and 120:
Detailed Example Design Chapter 13
Page 121 and 122:
Directory and File Contents The di
Page 123 and 124:
example_design/fifo Directory and F
Page 125 and 126:
simulation/functional Directory and
Page 127 and 128:
Implementation and Test Scripts Imp
Page 129 and 130:
10-Gigabit Ethernet MAC with Extern
Page 131 and 132:
10-Gigabit Ethernet MAC with 64-bit
Page 133 and 134:
AXI4-Lite to IPIF Converter Block X
Page 135 and 136:
Verification and Interoperability A
Page 137 and 138:
Appendix B Calculating the DCM Fixe
Page 139 and 140:
Core Latency Transmit Path Latency
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Xilinx UG773 LogiCORE IP 10-Gigabit Ethernet MAC v11.1, User ...

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