Video Surveillance Implementation Using FPGAs - Altera
Video Surveillance Implementation Using FPGAs - Altera
Video Surveillance Implementation Using FPGAs - Altera
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<strong>Altera</strong> Corporation <strong>Video</strong> <strong>Surveillance</strong> <strong>Implementation</strong> <strong>Using</strong> <strong>FPGAs</strong><br />
Encapsulation of the TS data for Ethernet uses IP and the user datagram protocol (UDP). Optionally, the real-time<br />
transport protocol (RTP) can also be used. Dedicated hardware performs the encapsulation, maximizing the<br />
throughput of the reference design and minimizing latency. Frames can be processed, transmitted, and received at the<br />
Ethernet line rate, which supports an aggregate TS bandwidth of over 900 Mbps for a gigabit Ethernet link. For<br />
multiple TS interfaces, the reference design individually maps each one to a specific UDP/IP socket (combination of<br />
IP address and UDP port). All other encapsulation parameters also can be individually configured per TS. The<br />
reference design supports IP multicast and includes a Nios ® II processor. Software running on the Nios II processor<br />
configures the operation of the reference design and handles any Ethernet management traffic.<br />
Systems Interfaces<br />
<strong>Altera</strong> and its partners offer several interface cores that are relevant to video surveillance systems. These include<br />
DDR2 SDR DRAM Controllers, ATA Hard Disk Drive Controller, and PCI Express.<br />
Benchmarks<br />
An 4-channel D1 solution or 16-channel CIF solution with H.264 baseline profile encoding, deinterlacing, scaling,<br />
color space conversion, and noise reduction using 2D FIR filtering can be implemented in <strong>Altera</strong>'s Cyclone III<br />
EP3C55 FPGA.<br />
Conclusion<br />
The ideal surveillance architecture will have the following characteristics: high performance, flexibility, easy<br />
upgradability, low development cost, and a migration path to lower cost as the application matures and volume<br />
ramps. <strong>Altera</strong>'s <strong>FPGAs</strong> in conjunction with the feature-rich <strong>Altera</strong> <strong>Video</strong> and Image Processing Suite, <strong>Altera</strong> <strong>Video</strong><br />
over IP reference design, and partner's compression solutions offer video system designers all the key building blocks<br />
needed to produce such a system.<br />
Further Information<br />
■ <strong>Altera</strong>'s <strong>Video</strong> and Image Processing Solutions website:<br />
www.altera.com\video_imaging<br />
■ <strong>Altera</strong>’s <strong>Video</strong> Processing Reference Design:<br />
www.altera.com/end-markets/refdesigns/sys-sol/broadcast/ref-post-processing.html<br />
Acknowledgements<br />
■ Tam Do, Senior Technical Marketing Manager, Broadcast/Automotive/Consumer Business Unit, <strong>Altera</strong><br />
Corporation<br />
101 Innovation Drive<br />
San Jose, CA 95134<br />
(408) 544-7000<br />
http://www.altera.com<br />
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