ELET 3132L - Lab #1

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24. Left click once on Auto-Separate then left click once on Apply then left click once on OK. You may also want to make your plot window larger and reverse the background. Your plot should now look like: Figure 11: All Traces 25. Choose File→Print to print the plot for your lab report. Close the plot window. Choose File→Print to print the schematic for your lab report. Choose File→Save All to save the entire DTL project in case you want to refer to it later. Close MultiSIM for now. SIMULATION (Part 2): PSpice 1. Now you will perform a similar simulation using PSpice. To start PSpice, select Start→All Programs→MosaicXP→Engineering→Electrical→Cadence PSpice→Capture CIS. It can take a half-minute or so to start (depends on how busy the MOSAIC network is). Eventually you will see a dialog box as Capture starts. Pick the PCB Design Studio with Capture CIS choice. Capture CIS is the schematic entry point to PSpice. Figure 12: Suite Selection ELET 3132L Experiment #1 8 of 25
2. When Capture starts, you will see a blank project. Choose File→New→Project to make a new project. You will see the following dialog box. Make sure you pick a directory on your H drive, choose Analog or Mixed A/D and type in a name for your project (I used CMOS). Figure 13: New Project Dialog Box 3. PAY ATTENTION: THIS IS IMPORTANT!! Capture is used for many different things from schematics to board design to simulation work. As such, it has many different parts libraries. You MUST use parts libraries that have PSpice simulation parameters. You will set the libraries up first so you have only PSpice parts in your design. 4. Similar to MultiSIM, select Place→Part from the top menu bar. This is where part libraries are specified for Capture. You will see a dialog box as shown below. The first thing to do is to remove all the “unPSpice” parts libraries. So select each library by left clicking once on it then left click on the Remove Library button to remove it. You cannot remove the Design Cache – that is a file used to cache parts for your design. When you have finished removing libraries the dialog box should look like Figure 14: Figure 14: PLACE PART Dialog Box ELET 3132L Experiment #1 9 of 25
Page 1 and 2: ELET 3132L - Lab #1 Logic Gates and
Page 3 and 4: Figure 3: Component Selection Dialo
Page 5 and 6: 15. Now you can add wires to connec
Page 7: 22. Left-click the Simulate button
Page 11 and 12: Figure 17: Completed Schematic 8. Y
Page 13 and 14: Figure 21: Values for the Signal Ge
Page 15 and 16: Figure 27: Placing Ground 21. For t
Page 17 and 18: Figure 31: Plot Menu 27. Now repeat
Page 19 and 20: Figure 35: Inverted Colors (Using P
Page 21 and 22: Logic Gates and Families You will b
Page 23 and 24: Steps 4 through 6: typical DTL (Dio
Page 25: QUESTIONS: 1. How does your lab dat

ELET 3132L - Lab #1

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