datasheet: pdf - svn

NXP Semiconductors HEF4094B
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 10. Test circuit
Table 10. Test data
VI
input pulse
VSS
10 %
G
tr
RT
8-stage shift-and-store bus register
001aag804
Supply voltage Input VEXT Load
VI
90 %
VDD VI tr, tf tPHL, tPLH tPHZ, tPZH tPLZ, tPZL CL RL
5 V to 15 V VSS or VDD ≤ 20 ns open VDD VSS 50 pF 1 kΩ
HEF4094B_4 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 04 — 30 October 2008 10 of 17
VDD
DUT
VO
tf
VEXT
RL
CL