datasheet: pdf - svn
datasheet: pdf - svn
datasheet: pdf - svn
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NXP Semiconductors HEF4094B<br />
11. Waveforms<br />
Measurement points are given in Table 9.<br />
Logic levels: VOL and VOH are typical output voltage drops that occur with the output load.<br />
Fig 6. Clock to outputs propagation delays, and clock pulse width and maximum frequency<br />
Table 9. Measurement points<br />
VI<br />
CP input VM<br />
QPn, QS1 output<br />
GND<br />
VOH<br />
VOL<br />
VOH<br />
VOL<br />
tPLH<br />
tW<br />
1/fmax<br />
VM<br />
8-stage shift-and-store bus register<br />
HEF4094B_4 © NXP B.V. 2008. All rights reserved.<br />
Product data sheet Rev. 04 — 30 October 2008 8 of 17<br />
tPLH<br />
QS2 output VM<br />
Supply voltage Input Output<br />
tPHL<br />
tPHL<br />
001aaf113<br />
VDD VM VM VX VY<br />
5 V to 15 V 0.5VDD 0.5VDD 0.1VDD 0.9VDD<br />
VI<br />
STR input VM<br />
QPn output<br />
GND<br />
VOH<br />
VOL<br />
Measurement points are given in Table 9.<br />
Logic levels: VOL and VOH are typical output voltage drops that occur with the output load.<br />
Fig 7. Strobe to output propagation delays, and strobe pulse width, set up and hold times<br />
tPLH<br />
tW<br />
VM<br />
tPHL<br />
001aaj058
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