MPC5668x Data Sheet - Freescale Semiconductor

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Pin assignments 3.2 Pin muxing and reset states Table 3 shows the signals properties for each pin on PXN20. For all port pins that have an associated SIU_PCRn register to control pin properties, the supported functions column lists the functions associated with the programming of the SIU_PCRn[PA] bit in the order: general-purpose input/output (GPIO), function 1, function 2, and function 3 (see Figure 5). When an alternate function is not implemented for a value of SIU_PCRn[PA], a dash is shown in the Description column and the respective value in the PA bit field is reserved. Pin Name 1 PA0 PA[0] AN[0] PA1 PA[1] AN[1] PA2 PA[2] AN[2] PA3 PA[3] AN[3] PA4 PA[4] AN[4] PA5 PA[5] AN[5] 8 Supported Functions 2 Supported Functions 2 PA[0] AN[0] GPIO (PCR) Num 3 PA 4 0 00 01 10 11 1 00 01 10 11 2 00 01 10 11 3 00 01 10 11 4 00 01 10 11 5 00 01 10 11 GPIO (PCR) Num 3 0 00 01 10 11 Figure 5. Supported functions example Table 3. PXN20 signal properties Description Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — PA 4 Description Port A GPI ADC Analog Input — — Port A (16) I/O Type I I — — I I — — I I — — I I — — I I — — I I — — Volt- age PXN20 Microcontroller Data Sheet, Rev. 1 GPIO Function 1 Functions 2 and 3 not implemented Pad Type 5 During Reset 6 Status After Reset 7 Package Pin Locations 208 BGA V DDA IHA — — D15 V DDA IHA — — E15 V DDA IHA — — F16 V DDA IHA — — F15 V DDA IHA — — G16 V DDA IHA — — G15 Freescale Semiconductor
Pin Name 1 PA6 PA[6] AN[6] PA7 PA[7] AN[7] PA8 PA[8] AN[8] PA9 PA[9] AN[9] Supported Functions 2 PA10 PA[10] AN[10] PA11 PA[11] AN[11] PA12 PA[12] AN[12] PA13 PA[13] AN[13] PA14 PA[14] AN[14] EXTAL32 PA15 PA[15] AN[15] XTAL32 GPIO (PCR) Num 3 PA 4 6 00 01 10 11 7 00 01 10 11 8 00 01 10 11 9 00 01 10 11 10 00 01 10 11 11 00 01 10 11 12 00 01 10 11 13 00 01 10 11 14 00 01 10 11 15 00 01 10 11 Table 3. PXN20 signal properties (continued) Description Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input — — Port A GPI ADC Analog Input External 32 kHz Crystal In — Port A GPI ADC Analog Input External 32 kHz Crystal Out — PXN20 Microcontroller Data Sheet, Rev. 1 Pin assignments Freescale Semiconductor 9 I/O Type I I — — I I — — I I — — I I — — I I — — I I — — I I — — I I — — I I I — I I O — Volt- age Pad Type 5 During Reset 6 Status After Reset 7 Package Pin Locations 208 BGA V DDA IHA — — H16 V DDA IHA — — G14 V DDA IHA — — F14 V DDA IHA — — E14 V DDA IHA — — D13 V DDA IHA — — E13 V DDA IHA — — D14 V DDA IHA — — F13 V DDA IHA — — D16 V DDA IHA — — E16
Page 1 and 2: Freescale Semiconductor Data Sheet:
Page 3 and 4: 1 Ordering information 1.1 Orderabl
Page 5 and 6: 2 PXN20 block diagrams Figure 2 sho
Page 7: 3 Pin assignments 3.1 208-ball MAPB
Page 11 and 12: Pin Name 1 Supported Functions 2 PB
Page 13 and 14: Pin Name 1 Supported Functions 2 PC
Page 15 and 16: Pin Name 1 Supported Functions 2 PE
Page 17 and 18: Pin Name 1 Supported Functions 2 PF
Page 19 and 20: Pin Name 1 Supported Functions 2 PG
Page 21 and 22: Pin Name 1 Supported Functions 2 PJ
Page 23 and 24: Pin Name 1 Supported Functions 2 PK
Page 25 and 26: 3.2.1 Power and ground supply summa
Page 27 and 28: 4.2 Thermal characteristics PXN20 M
Page 29 and 30: PXN20 Microcontroller Data Sheet, R
Page 31 and 32: 6 3.3-5.0 V External I/O Supply Vol
Page 33 and 34: 5 VDDSYN Current VDD33 @ 3.0V-3.6V
Page 35 and 36: 4.7.1 I/O pad V DD33 current specif
Page 37 and 38: 8 Crystal manufacturer’s recommen
Page 39 and 40: 4.11 ADC electrical characteristics
Page 41 and 42: Spec Pad Type 2 2 Medium 00 01 11 P
Page 43 and 44: 4.14 AC timing 4.14.1 Reset and boo
Page 45 and 46: TCK TMS, TDI TDO TCK JCOMP 4 5 7 8
Page 47 and 48: 4.14.4 Enhanced Modular I/O Subsyst
Page 49 and 50: SIN PCSx SCK Output (CPOL = 0) SCK
Page 51 and 52: PCSx SCK Output (CPOL = 0) SCK Outp
Page 53 and 54: 4.14.6 MLB Interface 4.14.6.1 Media
Page 55 and 56: Figure 23. Media Local Bus (MLB) ti
Page 57 and 58: Figure 26. MII async inputs timing
Page 59 and 60:
Figure 29. 208 MAPBGA package detai
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MPC5668x Data Sheet - Freescale Semiconductor

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