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Figure 3.1 Guest TLB for a core
d. Observe that the first translation entry is not 1-1 0x0c000000 -> 0x000100000.
Therefore, add the following command in the memory configuration file.
translate v:0x0c000000 p:0x00100000 0x00100000
Note that you do not need to add the translation entries that are already 1-1.
e. In case you find that TLB 0 also has non 1-1 translations and you want to access the respective
memory, go ahead and add the required translate command in the memory configuration file.
f. Display the guest tlb for another core, for example, gtlb 3 1, and check the TLB 1.
Figure 3.2 TLB 1 for another core
g. The first translation entry in the figure is the same that you added in the memory configuration file
in the previous steps. In addition, observe the non 1-1 entry 0x01000000 -> 0x002000000. Note
that this is the stack and is present in other SMP secondary cores. However, in this case, instruct
the debugger to access the 0x01000000- 0x01ffffff range by using virtual addresses. For example:
range v:0x01000000 v:0x01ffffff 4 ReadWrite LogicalData
h. Follow the same procedure to access the 0x00300000 - 0x0030ffff range. For example:
range v:0x00300000 v:0x0030ffff 4 ReadWrite LogicalData
34 Power Architecture® Processors Getting Started Guide