RTL Design Flow - Computation Structures Group

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Second Iteration Kurt Keutzer Fourth Iteration Kurt Keutzer A. Kahng A. Kahng 21 23 Third Iteration Kurt Keutzer Final Placement A. Kahng 22
Final Placement - 1 Earlier steps have broken down the problem into a manageable number of objects Two approaches: Kurt Keutzer Kurt Keutzer Final placement for standard cells/gate array – row assignment Final placement for large, irregularly sized macro-blocks – slicing – won’t talk about this Final Placement – Creating Rows 1 1 1 1,2 1,2 2 1,2 2,3 1,2 2,3 2 2,3 2,3 3 3 3 3,4 4 5 3,4 4 5 3,4 4 4,5 3,4 4 4,5 5 5 5 5 Row-based standard cell design Partitioning of circuit into 32 groups. Each group is either assigned to a single row or divided into 2 rows 25 27 Final Placement – Standard Cell <strong>Design</strong>s Kurt Keutzer This process continues until there are only a few cells in each group( ≈ 6 ) group: smallest partition each group has ≤ 6 cells Assign cells in each group close together in the same row or nearly in adjacent rows A. E. Dunlop, B. W. Kernighan, A procedure for placement of standard-cell VLSI circuits, IEEE Trans. on CAD, Vol. CAD-4, Jan , 1985, pp. 92- 98 Standard Cell Layout 28
Page 1 and 2: VLSI CAD Flow: Logic Synthesis, Pla
Page 3 and 4: Algebraic vs. Boolean Methods Algeb
Page 5 and 6: Tech.-Dependent Optimization LIBRAR
Page 7 and 8: DAG Covering Sound Algorithmic appr
Page 9 and 10: RTL Design Flow Library/ module gen
Page 11 and 12: Modeling the Net’s Wire Length (x
Page 13: Layout after Min-cut Now global pla
Page 17 and 18: Physical Design Flow Input Floorpla
Page 19: Graph Search Steiner Iterative ECE

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