RTL Design Flow - Computation Structures Group
RTL Design Flow - Computation Structures Group
RTL Design Flow - Computation Structures Group
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<strong>RTL</strong> <strong>Design</strong> <strong>Flow</strong><br />
Library/<br />
module<br />
generators<br />
HDL<br />
<strong>RTL</strong><br />
Synthesis<br />
netlist<br />
logic<br />
optimization<br />
netlist<br />
physical<br />
design<br />
layout<br />
manual<br />
design<br />
a 0 d<br />
b 1<br />
Results of Placement<br />
Kurt Keutzer<br />
A bad placement<br />
s<br />
clk<br />
a 0 d<br />
b 1<br />
What’s good about a good placement?<br />
What’s bad about a bad placement?<br />
s<br />
q<br />
clk<br />
q<br />
A good placement<br />
A. Kahng<br />
3<br />
Kurt Keutzer<br />
Physical <strong>Design</strong>: Overall Conceptual <strong>Flow</strong><br />
Input<br />
Floorplanning<br />
Placement<br />
Routing<br />
Output<br />
Read Netlist<br />
Floorplanning<br />
Initial Placement<br />
Routing Region<br />
Definition<br />
Global Routing<br />
Cost Estimation<br />
Routing Region<br />
Ordering<br />
Detailed Routing<br />
Cost Estimation<br />
Compaction/clean-up<br />
Write Layout Database<br />
Results of Placement<br />
Bad placement causes routing<br />
congestion resulting in:<br />
• Increases in circuit area (cost)<br />
and wiring<br />
• Longer wires more capacitance<br />
Longer delay<br />
Higher dynamic power<br />
dissipation<br />
Placement<br />
Improvement<br />
Routing<br />
Improvement<br />
Good placement<br />
•Circuit area (cost) and wiring<br />
decreases<br />
• Shorter wires less capacitance<br />
Shorter delay<br />
Less dynamic power<br />
dissipation<br />
4
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