RTL Design Flow - Computation Structures Group

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Optimum Tree Covering INV 2 NAND2 3 INV 11 + 2 = 13 NAND2 2 + 6 + 3 = 11 NAND2 3 + 3 = 6 NAND2 3 AOI21 4 + 3 = 7 29
RTL Design Flow Library/ module generators HDL RTL Synthesis netlist logic optimization netlist physical design layout manual design a 0 d b 1 Results of Placement Kurt Keutzer A bad placement s clk a 0 d b 1 What’s good about a good placement? What’s bad about a bad placement? s q clk q A good placement A. Kahng 3 Kurt Keutzer Physical Design: Overall Conceptual Flow Input Floorplanning Placement Routing Output Read Netlist Floorplanning Initial Placement Routing Region Definition Global Routing Cost Estimation Routing Region Ordering Detailed Routing Cost Estimation Compaction/clean-up Write Layout Database Results of Placement Bad placement causes routing congestion resulting in: • Increases in circuit area (cost) and wiring • Longer wires more capacitance Longer delay Higher dynamic power dissipation Placement Improvement Routing Improvement Good placement •Circuit area (cost) and wiring decreases • Shorter wires less capacitance Shorter delay Less dynamic power dissipation 4
Page 1 and 2: VLSI CAD Flow: Logic Synthesis, Pla
Page 3 and 4: Algebraic vs. Boolean Methods Algeb
Page 5 and 6: Tech.-Dependent Optimization LIBRAR
Page 7: DAG Covering Sound Algorithmic appr
Page 11 and 12: Modeling the Net’s Wire Length (x
Page 13 and 14: Layout after Min-cut Now global pla
Page 15 and 16: Final Placement - 1 Earlier steps h
Page 17 and 18: Physical Design Flow Input Floorpla
Page 19: Graph Search Steiner Iterative ECE

RTL Design Flow - Computation Structures Group

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