Bluespec: Why chip design can't be left EE's - MIT

More documents

Recommendations

Info

GCD Hardware Module implicit conditions Nikhil’s visualization enab rdy rdy 32 32 32 start result GCD module interface GCD; method Action start (int x, int y); method int result; endinterface 12
Generated Verilog RTL: GCD module mkGCD(CLK, RST_N,start__1, start__2, E_start_, ...) input CLK; ... output start__rdy; ... wire [31 : 0] x$get; ... assign result_ = x$get; assign _d5 = y$get == 32'd0; ... assign _d3 = x$get ^ 32'h80000000)
Page 1 and 2: Bluespec: Why chip design can’t b
Page 3 and 4: Pressing problems of chip design Pr
Page 5 and 6: Bluespec A Gap in Chip Design Desig
Page 7 and 8: Bluespec & SystemVerilog high (good
Page 9 and 10: Bluespec: State and Rules organized
Page 11: GCD in Bluespec module mkGCD (GCD);
Page 15 and 16: pc Processor Pipelines and FIFOs fe
Page 17 and 18: Rules for Add implicit checks: bu n
Page 19 and 20: Fetch & Decode Rule: corrected pc C
Page 21 and 22: Modular organization pc iMem RFile
Page 23 and 24: The “Arbiter” Project @ Sandbur
Page 25 and 26: Design Problem 64 Items: Index of I
Page 27 and 28: Some advanced features Connectables
Page 29 and 30: MIT work, 1997-2000 TRAC compiler (
Page 31 and 32: Contributors MIT Arvind Dan Rosen
Page 33 and 34: Extras 33
Page 35 and 36: Synthesis from Bluespec 35
Page 37 and 38: Scheduling and control logic Module
Page 39 and 40: Combining State Updates: strawman
Page 41 and 42: Miscellaneous slides 41
Page 43 and 44: Technology validation @ Sandburst M
Page 45: Key concept: “Push” interface,

Bluespec: Why chip design can't be left EE's - MIT

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?