Bluespec: Why chip design can't be left EE's - MIT

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Verification Solutions Assertions (Specman/Vera etc.) improve the productivity of the verification engineer but don’t address the root cause Design complexities increasing Verilog/VHDL has seen no fundamental enhancements in synthesis capability in almost 15 years Bluespec can change this. 42
Technology validation @ Sandburst Modeling of Hibeam chip set 12K lines of Bluespec code, accurate chip and block boundaries, accurate inter-chip & inter-block messaging Used for QoS algorithm analysis and validation This is the model of Sandburst's Hibeam chip set (there is no other C++ or SystemC model) Learning: capable of supporting large programs and models Synthesis – Mesa Project 2001 IP Packet lookup. Subset of a Sandburst Hibeam product chip; same tools, libraries ~ 8K lines Bluespec, ~ 400K gates, 3mm sq die, 185 MHz Included Verilog cores: on-chip memory, BIST, off-chip memory, jtag, scan, high-speed serial I/O, PCI bus, etc. Learning: fits comfortably in ecosystem of other tools Synthesis - Re-code product chip (“arbiter”) in Bluespec 2002 43
Page 1 and 2: Bluespec: Why chip design can’t b
Page 3 and 4: Pressing problems of chip design Pr
Page 5 and 6: Bluespec A Gap in Chip Design Desig
Page 7 and 8: Bluespec & SystemVerilog high (good
Page 9 and 10: Bluespec: State and Rules organized
Page 11 and 12: GCD in Bluespec module mkGCD (GCD);
Page 13 and 14: Generated Verilog RTL: GCD module m
Page 15 and 16: pc Processor Pipelines and FIFOs fe
Page 17 and 18: Rules for Add implicit checks: bu n
Page 19 and 20: Fetch & Decode Rule: corrected pc C
Page 21 and 22: Modular organization pc iMem RFile
Page 23 and 24: The “Arbiter” Project @ Sandbur
Page 25 and 26: Design Problem 64 Items: Index of I
Page 27 and 28: Some advanced features Connectables
Page 29 and 30: MIT work, 1997-2000 TRAC compiler (
Page 31 and 32: Contributors MIT Arvind Dan Rosen
Page 33 and 34: Extras 33
Page 35 and 36: Synthesis from Bluespec 35
Page 37 and 38: Scheduling and control logic Module
Page 39 and 40: Combining State Updates: strawman
Page 41: Miscellaneous slides 41
Page 45: Key concept: “Push” interface,

Bluespec: Why chip design can't be left EE's - MIT

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