Bluespec: Why chip design can't be left EE's - MIT

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10 Gbs/line Multicast Arbiter ingress nodes . . . . . . egress nodes egress set priorites: #1 #2 #3 1. find highest-priority valid egress set for each ingress 2. remove all but highest-priority of conflicting grants 24
Design Problem 64 Items: Index of Item with Max Value maxs maxs maxs maxs maxs maxs Push> indexOfMax = pass ( maxs ) >> pass ( maxs ) >> pass ( maxs ) >> pass ( maxs ) >> pass ( maxs ) >> pass ( maxs ) >> pass ( get_index ) >> tramToPush ( emapMem ); outputMemValue; Memory Lookup maxs: takes a list & compares priority of adjacent pairs, return list of half the size 25
Page 1 and 2: Bluespec: Why chip design can’t b
Page 3 and 4: Pressing problems of chip design Pr
Page 5 and 6: Bluespec A Gap in Chip Design Desig
Page 7 and 8: Bluespec & SystemVerilog high (good
Page 9 and 10: Bluespec: State and Rules organized
Page 11 and 12: GCD in Bluespec module mkGCD (GCD);
Page 13 and 14: Generated Verilog RTL: GCD module m
Page 15 and 16: pc Processor Pipelines and FIFOs fe
Page 17 and 18: Rules for Add implicit checks: bu n
Page 19 and 20: Fetch & Decode Rule: corrected pc C
Page 21 and 22: Modular organization pc iMem RFile
Page 23: The “Arbiter” Project @ Sandbur
Page 27 and 28: Some advanced features Connectables
Page 29 and 30: MIT work, 1997-2000 TRAC compiler (
Page 31 and 32: Contributors MIT Arvind Dan Rosen
Page 33 and 34: Extras 33
Page 35 and 36: Synthesis from Bluespec 35
Page 37 and 38: Scheduling and control logic Module
Page 39 and 40: Combining State Updates: strawman
Page 41 and 42: Miscellaneous slides 41
Page 43 and 44: Technology validation @ Sandburst M
Page 45: Key concept: “Push” interface,

Bluespec: Why chip design can't be left EE's - MIT

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